Patents Assigned to F.T.L. Co., LTD
  • Publication number: 20120202352
    Abstract: A vertical single wall reaction tube type batch processing furnace can reduce the generation of particles. A method of removing native oxide film by fluoride gas can enhance the efficiency of utilization of gas. A method of exciting reaction gas by a catalyst at high temperature can be applied to a batch processing. A method of exciting reaction gas by a catalyst utilizes an oxidizing agent and gas other than an oxidizing agent. The flow rate of gas in the gas injection pipe and that of gas in the exhaust pipe are made to be substantially equal to each other. The gap between two adjacent wafers is made greater than the mean free path of gas. The oxidizing agent is dissociated by a catalyst of Ir, V or Kanthal while the gas other than the oxidizing agent is dissociated by a catalyst of W.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 9, 2012
    Applicant: F.T.L. CO., LTD.
    Inventor: Mikio TAKAGI
  • Patent number: 8097541
    Abstract: Native oxide film on a semiconductor silicon wafer(s) is dry etched at a temperature of 50° C. or less. Hydrogen treatment is then carried out a temperature of 100° C. or more to bond the dangling bonds with hydrogen. A jig 9 that has been used is again used for loading new semiconductor silicon wafer(s) 10. The wafer(s) on the jig 9 is subjected to removal of a native oxide film and then hydrogen bonding. The resultant heat remains in jig and makes it difficult to maintain the wafers to temperature appropriate to removal of a native oxide film. After treatment of hydrogen bonding, inert gas having temperature of from 0 to ?30° C. is injected into reaction vessel 5 and/or treatment preparing vessel 21, in which a native oxide film has been removed.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: January 17, 2012
    Assignees: F.T.L. Co., Ltd., ULVAC, Inc.
    Inventors: Mikio Takagi, Seiichi Takahashi, Hiroaki Inoue, Masayuki Satou, Yutaka Miura
  • Patent number: 6867147
    Abstract: A method of removing native oxide film from contact holes of a semiconductor device by using a microwave-excited reactive gas. The method increases throughput. Reactive gas is introduced substantially horizontally into the reactor (20) by way of a chamber (5, 22) arranged as an extension thereof in the vertical direction of the reactor (20) and showing an internal pressure higher than that of the reactor, while the plurality of semiconductor silicon wafers (10) that are arranged in the vertical direction and held to temperature not higher than 323 K are being rotated, and subsequently said reactor is heated (30) to above 373 K.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: March 15, 2005
    Assignee: F.T.L. Co., LTD
    Inventor: Mikio Takagi
  • Patent number: 6793734
    Abstract: An assembly of heating furnace and semiconductor wafer-holding jig. This assembly includes a furnace body made of refractory or heat insulting material; a heater disposed around the inner side surface of the furnace body; a reaction chamber which forms a uniform heating zone; and a wafer-holding jig. The wafer-holding jig is capable of holding the wafer and advancing and retracting the wafer in the uniform heating region along the longitudinal direction of the furnace body. The front surface of the semiconductor wafer to be heat-treated is substantially in parallel with the surface of the heater. The assembly of the invention can be used in rapid thermal processing and the footprint of the heating furnace can be reduced.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: September 21, 2004
    Assignees: F.T.L. Co., Ltd., Topco Scietific Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 6248672
    Abstract: In a method for producing a semiconductor device using a dual tube reactor, inert gas is fed into the vertical reaction-tube, a reaction gas is introduced into the vertical reaction-tube, the inert gas is exhausted through the annular channel formed between the inner tube and the outer tube at a bottom portion of the vertical reaction-tube; and, a wafer is heat treated in the vertical reaction-tube by means of a heating furnace. In order to decrease the number and size of the particles, the wafer is displaced upward and then positioned at a level substantially the same as or above the top end of the inner tube, and the reaction gas is introduced into the vertical reaction-tube at or above the position of the wafer. Furthermore, the inert gas is caused to flow from a bottom portion of the inner tube toward the wafer positioned as above. As a result, inflow of the reaction gas into the inner tube is impeded, and the generation of particles there can be lessened.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: June 19, 2001
    Assignee: F.T.L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 6204194
    Abstract: The film growth speed of a conventional vertical heating method, such as SiO2 film, polycrystalline Si film or the like of a semiconductor device, is enhanced by means of discharging and sucking the reaction gas onto and from the Si wafers placed horizontally in the vertical furnace. The wafers are rotated and the wafer-distance is set at 5 mm or more.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: March 20, 2001
    Assignee: F.T.L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 6159873
    Abstract: In a RTP (rapid Thermal Processing) of a large-diameter semiconductor wafer using a hot-wall type heating furnace, the temperature distribution of the wafer surface is made uniform by means of preliminarily heating a thermal storage plate(s) to a heat-treating temperature, and, then positioning the wafer between a pair of the thermal storage plates or in the direct proximity of a thermal storage plate. The wafer may be brought into contact with the thermal storage plate. The wafer is thus heated rapidly heated to the heat treating temperature.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: December 12, 2000
    Assignee: F.T.L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 5643839
    Abstract: In a rapid thermal processing (RTP) of a large-diameter wafer, a wafer is heat treated by an upper high-temperature furnace and a lower low-temperature furnace, which are separated from and can be brought into close contact with one another by a relative vertical position adjusting means. The upper high-temperature furnace has an open bottom which is shut by an openable, heat insulating shutter. Height of the apparatus as a whole can be shortened.
    Type: Grant
    Filed: January 25, 1995
    Date of Patent: July 1, 1997
    Assignee: F.T.L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 5445676
    Abstract: A wafer(s) for producing semiconductor devices is subjected to heat treatment in a vertical thermal reactor, which is provided with an electric heating means setting a first temperature and another electric heating means setting a second temperature higher than the first temperature. The wafer(s) is moved upwards and is subjected to a treatment in the second region of the vertical thermal reactor; and, is reverted to the first region. Rapid thermal processing of 6 or 8 inch wafer(s) is possible without causing slip lines.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: August 29, 1995
    Assignee: F.T.L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 5407485
    Abstract: In a rapid thermal processing (RTP) of a large-diameter wafer, a wafer is heat treated by an upper high-temperature furnace and a lower low-temperature furnace, which are separated from and can be brought into close contact with one another by a relative vertical position adjusting means. The upper high-temperature furnace has an open bottom which is shut by an openable, heat insulating shutter. Height of the apparatus as a whole can be shortened.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: April 18, 1995
    Assignee: F. T. L. Co., Ltd.
    Inventor: Mikio Takagi
  • Patent number: 5387557
    Abstract: A wafer(s) for producing semiconductor devices is subjected to heat treatment in a vertical thermal reactor, which is provided with an electric heating means setting a first temperature and another electric heating means setting a second temperature higher than the first temperature. The wafer(s) is moved upwards and is subected to a treatment in the second region of the vertical thermal reactor; and, is reverted to the first region. Rapid thermal processing of 6 or 8 inch wafer(s) is possbile without causing slip lines.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: February 7, 1995
    Assignee: F. T. L. Co., Ltd.
    Inventor: Mikio Takagi