Abstract: A titanium-nickel-palladium solderable metal system for silicon power semiconductor devices (10), which may be used for one or both of the anode (20) or cathode (30). The metal system includes an outer layer of palladium (40,70), an intermediate layer of nickel (50,80), and an inner layer of titanium (60,90). For certain applications, the nickel may be alloyed with vanadium. The metal system may be deposited on bare silicon (100) or on one or more additional layers of metal (110) which may include aluminum, aluminum having approximately 1% silicon, or metal silicide. The use of palladium, rather than gold or silver, reduces cost, corrosion, and scratching.

Abstract: A high-efficiency power semiconductor rectifier device (10) comprising a ?P++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the ?P++ layer (12) of supersaturated P-doped silicon.

Abstract: A rectifier device (10) comprising a multi-layer epitaxial film (12) and a rectifier and a transistor manufactured in the film (12), wherein the transistor is oriented vertically relative to the plane of the rectifier. The rectifier and transistor are separated by a transition zone of inverted bias. The rectifier is a Schottky barrier rectifier, and the transistor is a JFET. More specifically, the device (1) comprises the film (12), a trench (16), a first region (18) associated with an upper portion of the trench (16), and second region (20) associated with a lower portion. The interface between the p+ material of the second region (20) and the n material of the film (12) creates a p+/n junction. The device (10) has use in high frequency, low-loss power circuit applications in which high switching speed and low forward voltage drop are desirable.

Abstract: A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystalline growth forms the substrate layer (22), and this high quality crystal is used as the high resistivity layer in the device (20). The base layer (24) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface (32) of the substrate layer (22) at a fast rate greater than approximately 2 microns/minute. The top layer (26) is a diffusion layer diffused into an upper surface (34) of the substrate layer (22). To control stress in the wafer (28), the epitaxial base is doped with germanium.

Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.

Abstract: The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device.

Abstract: An apparatus and method for delivering power from a D.C. voltage source to one or more D.C. loads rated at lower voltages. The invention provides for the repetitive application of the higher D.C. voltage to the loads for a predetermined time period sufficient for the load to operate yet not too long to ensure that the load will not be damaged. To implement the invention, a clock signal provides the time reference for separate slots allocated for the time periods associated with each of the loads. A user selectively enables or interrupts the repetitive connection to each of one of the loads. The rate of repetition of the connection of the high voltage source could vary from 60 to 200 Hertz, preferably without degrading the operation of typical loads.

Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.

Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: A single step etched moat (24), having a regular grid work mask (28) of mesa shields (42) and edge termination shields (44), is utilized to form, in a single etching step, semiconductor devices (22) having lengthy edge terminations for reduced edge termination failure. The desired semiconductor devices (22) include a high resistivity, monocrystalline grown substrate layer (30), a low resistivity epitaxial base layer (32), and a low resistivity top layer (36). The regular grid work of mesa shields (42) and edge termination shields (44) define open grid lines (48) and open grid rings (46). The open grid lines (48) are wider than the open grid rings (46), so that as the moats (24) are etched, a deeper grid line divot (50) is formed below the open grid lines (48) and a more shallow grid ring divot is formed below the open grid ring (46).