Abstract: Disclosed is a power loss protection integrated circuit. According to one embodiment, the power loss protection integrated circuit includes a buck/boost converter controller that operates in buck mode in a normal power supply state such that a portion of the power is used to store energy in a low voltage capacitor and operates in boost mode when the power supply is cut off such that the energy charged in the low voltage capacitor is utilized to supply emergency power to a main system.

Abstract: Discloses is an inrush current limiting circuit for a power system. In the power system that charges an output capacitor when an input voltage is initially applied and in which multiple resistance elements and switching elements are connected in an electrical path that connects the input voltage and an output voltage, the inrush current limiting circuit for the power system implements the soft start of the power system by limiting a peak value of an input current to a predetermined level or less by changing a total resistance value of the electrical path through an operation of the switching elements.

Abstract: Disclosed is a soft start circuit 100 for a power system 1. In the soft start circuit 100, an input voltage VIN is applied to charge an output capacitor COUT and output an output voltage VOUT such that a soft start of the power system 1 is achieved. A constant current is supplied onto an electrical path connecting the input voltage VIN and the output voltage VOUT to charge the output capacitor COUT at the soft start time.

Abstract: Disclosed is a DC/DC converter using an adaptive controller for maximum efficiency under dynamic load conditions. The DC/DC converter includes N power switches, each of which has a size of 1/N such that their device size is maintained the same as that of power switches of a conventional DC/DC converter. The use of the adaptive controller in the DC/DC converter can achieve maximum efficiency under dynamic load conditions by varying the number of power switches driven depending on load currents.

Abstract: A method of characterizing an error in a NAND flash memory, and an error estimation method and a storage system control method using the same are provided. The method of characterizing an error in a NAND flash memory characterizes an error source of the NAND flash memory using a center distance between one pattern and another pattern among a plurality of patterns in a threshold voltage distribution of NAND flash memory cells as a parameter.

Abstract: A power loss protection integrated circuit is disclosed. The power loss protection integrated circuit includes separate charge/discharge paths to a plurality of storage capacitors to enable sequential checking of the plurality of storage capacitors for short failure. When any one of the storage capacitors has a short failure, charging of the corresponding storage capacitor is stopped. The plurality of storage capacitors are sequentially checked for deterioration after charge.

Abstract: Disclosed is a system for checking the capacity of a storage capacitor with high resolution. The system is constructed to increase the precision of correlation between a sink current and a clock frequency necessary for health check of the storage capacitor. This construction enables completion of the health check in a shorter time, minimizing both energy consumption and loss of the storage capacitor. Therefore, the system can supply sufficient energy as emergency power to a main system in an emergency power situation in which power supply is cut off.

Abstract: Disclosed is a power loss protection integrated circuit. In the power loss protection integrated circuit, an interrupt device is arranged on an electrical path between an output terminal of a buck converter and a low voltage capacitor such that a flow of current to the low voltage capacitor is limited upon initial operation to ensure stability of an output voltage of the buck converter, and after the passage of a predetermined time, the interrupt device is fully turned on when a voltage of the low voltage capacitor is almost the same as the output voltage of the buck converter such that the voltage of the low voltage capacitor is electrically connected to the output voltage of the buck converter.

Abstract: Disclosed is a power loss protection integrated circuit. In the power loss protection integrated circuit, an interrupt device is arranged on an electrical path between an output terminal of a buck converter and a low voltage capacitor such that a flow of current to the low voltage capacitor is limited upon initial operation to ensure stability of an output voltage of the buck converter, and after the passage of a predetermined time, the interrupt device is fully turned on when a voltage of the low voltage capacitor is almost the same as the output voltage of the buck converter such that the voltage of the low voltage capacitor is electrically connected to the output voltage of the buck converter.

Abstract: The present invention relates to a direct current/direct current (DC/DC) converter. According to the present invention, output ends of a plurality of converter circuits, each having two switches in a single fabricated integrated circuit (IC), are integrated by selectively connecting them to each other in the outside depending on the amount of current required for operation of the IC. Therefore, the DC/DC converter can operate with maximum efficiency in various user-desired load current ranges.

Abstract: Disclosed is a power loss protection integrated circuit. According to one embodiment, the power loss protection integrated circuit includes a buck/boost converter controller that operates in buck mode in a normal power supply state such that a portion of the power is used to store energy in a low voltage capacitor and operates in boost mode when the power supply is cut off such that the energy charged in the low voltage capacitor is utilized to supply emergency power to a main system.

Abstract: A method of characterizing an error in a NAND flash memory, and an error estimation method and a storage system control method using the same are provided. The method of characterizing an error in a NAND flash memory characterizes an error source of the NAND flash memory using a center distance between one pattern and another pattern among a plurality of patterns in a threshold voltage distribution of NAND flash memory cells as a parameter.

Abstract: A memory controller and a storage device including the same are provided. The memory controller generates a plurality of scrambled data by randomizing input data, counts the number of toggles per bit of each scrambled data, and writes one scrambled data with a smallest number of toggles in a non-volatile memory.

Abstract: A memory controller and a storage device including the same are provided. The memory controller for performing a buffering operation of temporarily storing data to be written to a non-volatile memory and data to be read from the non-volatile memory in a buffer memory includes a buffer request queue configured to store a plurality of buffer write requests requesting data to be temporarily stored in the buffer memory and a plurality of buffer read requests requesting data stored in the buffer memory to be read, a buffer traffic monitor configured to calculate the total amount of requested data in real time by summing the lengths of data specified in the respective buffer write requests and the respective buffer read requests stored in the buffer request queue, and a buffer manager configured to control execution of the buffering operation by setting an execution ratio based on the total amount of requested data calculated in real time.

Abstract: A memory controller and a storage device including the same are provided. The memory controller includes memory channel controllers configured to perform erase, program, read, erase suspend and program suspend operations for flash memories, a flash translation layer configured to control the memory channel controllers to process write/read commands, allocate a buffer space in a buffer memory in response to a write command in the write/read commands, temporarily store data in the allocated buffer space, and deallocate the buffer spaceaafter the data is programmed to the flash memory, a host interface configured to receive the write/read commands from a host and transmit the received write/read commands to the flash translation layer, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the size of the allocable buffer space, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.

Abstract: A memory controller and a storage device including the same are provided. The memory controller is provided with an internal memory in addition to an external memory for write buffering, and may manage a buffer in different modes according to the write workload of a host.

Abstract: A memory controller and a storage device including the same are provided. The memory controller is provided with an internal memory in addition to an external memory for write buffering. Accordingly, the frequency of accessing the external memory may be reduced.

Abstract: A memory controller and a storage device including the same are provided. The memory controller performs decoding by selecting a decoder of a level enough to correct bit errors in a codeword from among a plurality of error correction code (ECC) decoders based on a bit error history of a non-volatile memory device.

Abstract: A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.

Abstract: A memory controller and a storage device including the same are provided. The memory controller groups pages in a memory block into page groups of different classes according to bit error rates, and allocates a page to be programmed according to a reliability requirement of a logical block address (LBA).