Abstract: A line scan image sensor capable of operating at several different spatial sampling frequencies is provided by utilizing a line scanning array having sampling photoelements of different surface areas. The spatial sampling frequency of the sensor can be varied by selectively combining the charge packets generated by the individual photoelements. In a preferred embodiment, photoelements having two different surface areas are used, with the ratio of the smaller surface area with respect to the larger surface area being 1:.sqroot.2. A programmable amplifier is provided to normalize the outputs of photoelements having different surface areas so that a uniform illumination on different photoelements will produce a uniform response. The programmable amplifier can also be programmed to equalize the outputs of the sensor between the different spatial sampling frequency modes.

Abstract: A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

Abstract: A subsystem component for use in an image processing system to compute a gray scale histogram function or various statistical functions relating to the coordinates of a region or regions in a binary image. A selected function is computed at the video rate of frame generation.

Abstract: A high precision digital to analog converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compenate for errors of any bit combination. In a specific embodiment employing feedforward compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A temperature compensated sense amplifier is connected to the sense node of a memory array which is OR tied to the bit lines of the array. A PNP current mirror supplies voltage independent controlled current to the sense node. A level shifting stage is connected to the sense node to establish a threshold sensing level, and to switch on to steer the current into the amplifier stage. A compensation stage is connected to the level shifting stage and the amplifier stage to compensate for the .beta. factors of the transistors and the resistive changes with temperature. A temperature compensated current sink is connected to the PNP current mirror to track over temperature in opposition therewith and maintain a constant current into the sense node. The level shifting stage and the amplifier stage also include temperature compensating features to provide a sensing threshold which tracks constantly over the operating temperature range.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: A programmable charge coupled device transversal filter 5 includes a charge coupled device register 10 for receiving and delaying incoming analog signals, a series of floating gate charge detectors 15, a corresponding number of sets of binary scaled capacitors C.sub.0, . . . 2C.sub.0 . . . 2.sup.n C.sub.0, an output circuit including a positive and negative bus coupled to a differential amplifier, and mask or otherwise definable electrical connections for connecting selected ones of the scaled sets of capacitors between the floating gate 15 corresponding to that set and one of the positive and negative buses 22 and 23.

Abstract: A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

Abstract: A lead wire bonding machine is described for ball bonding the end of a lead wire held in a bonding tool to a die pad of an integrated circuit chip and for wedge bonding a segment of the lead wire spaced from the ball bond to a lead frame finger during successive ball bond wedge bond cycles. The bonding machine includes a variable linear drive such as a solenoid or small linear motor coupled to the bonding head for applying the first bond force to the bonding tool during ball bonding and the second bond force to the bonding tool during wedge bonding. A control circuit coupled to the solenoid or other variable linear drive delivers a first current having a desired profile or amplitude wave envelope for applying the first bond force with a first force profile during ball bonding to die pads and by delivering a second current having a desired profile or amplitude wave form for applying the second bond force with a second force profile during wedge bonding to lead frame fingers.

Abstract: An improved lead wire ball bonding machine for bonding wire leads between an integrated circuit chip and the lead frame on which the chip is mounted is provided with a bonding tool position sensor coupled to receive the Z-motion velocity waveform signal to the servo motor which drives the bonding head and bonding tool. This sensor detects the signal level and direction of change or polarity of the Z-motion velocity waveform signal for determining the location of the bonding head and bonding tool. The bonding tool position sensor is coupled and adjusted for generating a first output signal corresponding to a first location of the bonding head and bonding tool during motion downward to the die pad of an integrated circuit chip prior to contact by the bonding tool and lead wire for ball bonding.

Abstract: A self-aligned element antiblooming structure for application to charge-coupled devices includes a region in the substrate in which the charge-coupled device is fabricated into which both a P and N conductivity type impurity are introduced. By introducing impurities of different diffusivities, a sink region is created between two very narrow antiblooming barriers. Using appropriate process controls, the potential height of the antiblooming barriers may be adjusted to drain excess charge accumulating in the substrate adjacent the antiblooming barriers. In this manner the antiblooming function is accomplished using only a minimal area of the substrate. The invention is applicable to charge-coupled devices utilizing a variety of different clocking schemes, and to charge-coupled device image sensors using buried channels.

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I.sub.D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I.sub.D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I.sub.D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers.

Abstract: A method of defining narrow regions in an underlying integrated circuit structure includes the steps of depositing a first layer of material 30 having selected etching characteristics on the underlying integrated circuit structure, depositing a second layer of material 32 having etching characteristics different from the first layer 30 on the first layer 30, anisotropically etching the first layer 30 and the second layer 32 from all of the underlying integrated circuit structure 26 except for a desired region having a periphery which includes the narrow region, forming a coating 35 of smoothing material over all of the underlying integrated circuit structure 26 except for the first layer 30, and isotropically etching the first layer 30 to remove it from the surface of the underlying integrated circuit structure 26 to thereby define the narrow region 36. Use of the process to fabricate a compact bipolar transistor structure is also disclosed.

Abstract: A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address.

Abstract: A disabling circuit 71 responsive to a control signal 81 generated by applying to an IC pin 86 a signal outside the range of normal operating voltages of the device 16. The disabling circuit 71 grounds the output of are dundant address decoder such as 31 to disable a spare element 37 of the device 16, allowing identification of repaired elements.

Abstract: An improved method for forming a titanium silicide layer comprising placing a silicon layer overcoated with titanium in an ambient atmosphere of ultrapure nitrogen and heating the overcoated layer with radiation from a tungsten-halogen source.

Abstract: A high speed error correcting random access memory system includes a circuit for generation of a plurality of parity bits from a predetermined combination of data bits of a data word being stored in a random access memory such that these parity bits are stored in memory along with said data bits, and for outputting the data word from said memory system, including correcting for any single bit error in the data word, by a circuit that generates a check word from the data word bits and parity word bits stored in the memory, whose state indicates if any of the data bits are in error, and, if so, proceeds to correct any such erroneous bit. The system also includes a circuit for inserting an erroneous bit of data in memory after the parity bits have been generated, to check operation of the check word generating and output data word correction circuit. The operation of the check word generating circuit can also be suspended so as to enable uncorrected data words to be output by the memory system.