Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the die serves as a drain connection while the solder balls serve as the source and gate connections.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: A multiplexer with inhibit is implemented so that an active inhibit signal effectively sets the select signals to block all but the selected input signal and effectively masks the selected input signal. In the case of the disclosed emitter-coupled logic 4:1 multiplexer, enable signal controlled transistors (Q24 and Q25) are in parallel with transistors (Q14 and Q15) respectively controlled by the select signals (S0 and S1). Activating the enable signal (EN) effectively selects one input (A3) and blocks the others (A0, A1 and A2). A third enable activated transistor (Q35) is in parallel with the transistor (Q13) controlled by the selected input (A3). The activated enable masks the selected signal to complete the inhibit function. Thus, a standard function is implemented with a reduced free-standing and total transistor count.

Abstract: A two-level series gating complementary output master-slave D-type flip-flop (100) with multiplexed input incorporates a novel current-splitting network (108). The flip-flop includes a master latch (102), a slave latch (104) and a 2:1 multiplexer (106) incorporated into the master latch. The multiplexer includes a pair of matched, emitter-coupled, collector-uncoupled transistors (Q12 and Q13), the bases of which are tied to a reference voltage (VBB2). When a clock pulse (CP) is low, substantial network current flows through both matched transistors. This arrangement allows the circuit function to be implemented with a reduced transistor count and only two current sources. The master latch output (QM) is determined by the voltage at the base of an output transistor (Q21), which voltage is determined by the presence or absence of a current through a load resistor (RL1).