Abstract: This document discusses, among other things, a system and method for receiving an input signal and power supply information, and amplifying the input signal by a gain value determined as a function of the power supply information.

Abstract: A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the device was fabricated on just the surface of the wafer. Masking is avoided while open trenches are present. A transistor with a very low on-resistance per unit area is obtained.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.