Abstract: A dedicated hardware block in the form of a hardware bit coder device for generating IR/RF bit coding protocols. The hardware bit coder device is configurable to any user-defined frame length and single or multiple frame strings. The device can emulate substantially any desired bit coding pattern. The device uses a programmable signal shaping technique that eliminates the need to develop complex bit coding protocols in software. Using the hardware bit coder device of the present invention directly reduces the amount of program memory required by the microcontrollers to accomplish data decoding and also frees up the microcontroller resources for other purposes. The hardware bit coder includes a set of two pattern registers, one corresponding to a high data bit value and the other to a low data bit value. The particular pattern to be shifted out for transmission is defined by the particular data signal. Pattern transmission rate and period are selectable.

Abstract: A semiconductor substrate is provided that exhibits very low substrate resistance while also providing structural integrity and robustness to resist breakage during manufacturing. The invention also provides methods of making these semiconductor substrates. The semiconductor substrate includes a planar surface and a recess extending below the planar surface. Preferred substrates include a plurality of recesses arranged in an array.

Abstract: A wide-band, high-order, programmable video filter is implemented using transimpedance-based active integrators. An input voltage which may for instance represent a composite video signal is converted to a current in a linear manner using resistors and provided to a current amplifier at low impedance virtual ground nodes. The current is multiplied by a gain factor .beta..sub.R within the current amplifier and supplied to integrating capacitors connected in a feedback configuration around a high input impedance differential amplifier to establish an integrated differential voltage output. The transimpedance-based active integrators may be interconnected to realize wide-band, high-order video filters suitable for use in accordance with CCIR 601 standards. Input voltage swings are not restricted by a transistor's limited range of linear operation or voltage swing limitations of internal nodes but rather may allowed to swing as long as the bias currents sustain input current excursions.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a pseudo low-potential power rail. The pseudo low-potential rail is coupled to one arbiter circuit associated with one of the two circuit transfer nodes and a second arbiter circuit associated with the other of the two transfer nodes. The arbiter circuits are coupled to their respective nodes or pads and to a common low-potential supply rail. The arbiter selects for coupling to the pseudo low-potential rail the signal of the lower potential between that at the pad and that of the low-potential rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions.

Abstract: An monolithic programmable dc--dc converter controller integrated circuit with a high speed synchronous controller and a 4-bit programmable DAC to provide an operating voltage to an external device such as a microprocessor in response to a code programmed in the external device. The 4-bit programmable DAC outputs a signal which is combined with a precise reference voltage to provide voltages to the external device in increments of 100 millivolts.

Abstract: A CMOS rail-to-rail input/output operational amplifier has constant supply current with respect to the input signal's common mode voltage. By use of current bleeders, i.e. a smaller transistor of opposite conductivity type connected in parallel with each transistor in the differential pair of transistors, there is provided constant transconductance and constant supply current for rail-to-rail operation with respect to the positive and negative supply voltages. This allows production of a low cost, high performance and small area rail-to-rail input/output operational amplifier.

Abstract: An automated dynamic threshold testing system using an oscilloscope and personal computer with an automated testing algorithm for dynamic threshold condition determination within a digital logic device. The system provides a cost-effective alternative to conventional human detection of the threshold condition. The automated testing utilizes digitization of waveform data from the oscilloscope and provides fast storage, retrieval, and analysis of complex and numerous threshold conditions. Reproduction of the testings is easily performed with advantageous applications in debugging and diagnostic procedures.

Abstract: A difference capture circuit for determining the duration of a digital signal pulse. The difference circuit includes a branch couplable to a standard counter for activating the counter to count as a function of a system clock pulse, and a triggering circuit couplable to a standard capture register for fetching the count from the counter. The difference capture circuit may be incorporated into standard timer unit circuitry and is designed to calculate the difference between either the rise and fall times for an incoming signal, or the rise to rise time of that signal. Adding the difference capture circuit to a timing unit eliminates the need to use RAM, and minimizes processor resources, in obtaining the timing associated with a signal change.

Abstract: Die attach methods are provided. These methods include (a) providing a supply of die attach adhesive, (b) applying a portion of the die attach adhesive to a transfer member, and (c) contacting the lead frame paddle with the transfer member to print a layer of adhesive onto the lead frame paddle. Integrated circuit (IC) devices are also provided.

Abstract: A programmable DC-DC converter controller with a high speed synchronous controller and a 5-bit programmable DAC provides an operating voltage to an external device (such as a microprocessor) in response to a 5 bit code programmed in the external device. The 5-bit programmable DAC outputs a signal which provides voltages to the external device in increments of e.g. 50 or 100 millivolts, in respectively two different voltage ranges.

Abstract: A semiconductor integrated circuit to provide a low distortion, large swing intermediate frequency wherein the circuit includes the function of mixing, filtering, and amplification on a single chip. A pair of differential currents are obtained from the mixer, the differential currents are filtered and conditioned, converted to a pair of differential voltages and amplified to obtain the low distortion, large swing intermediate frequency.

Abstract: A digital-data-transmission-line circuit for actively clamping transmission signal and signal-complement amplitudes so as to reduce pattern-related jitter at a receiver/analyzer. The circuit includes a pair of opposing diode devices, where each diode device is coupled across the pair of conducting wires that make up the transmission line. The diode devices clamp the difference in potential between the two transmission lines so that the signal amplitude seen at the receiver will not vary to significantly with the number of like pulses that are transmitted in succession. In this manner, the present invention reduces pattern-dependent jitter in the cross-over from HIGH to LOW as seen at the receiver. By means of the parasitic capacitance accompanying the diode devices, the circuit of the present invention additionally provides some high-frequency filtering and smoothing of the waveform of the received signal.

Abstract: A dual adjustable voltage regulator combining a DC--DC switching regulator with a linear regulator implemented on a single chip is disclosed. The invention provides switching circuitry that can select between a fixed output voltage level and a user-adjustable output voltage. The circuit further provides means to automatically detect and generate power supply voltage levels as required by the system.

Abstract: A method and apparatus for adjusting charging and discharging currents of a pin driver to optimize slew rates and overshoot for different types of logic circuits. The current charging and discharging circuits include respective transistors that are mirrored to a transistor whose current varies in accordance with VH-VL where VH and VL are programmed reference voltages defining the high and low voltage levels of the output driver pulses. Thus, when VH-VL is relatively large such as for CMOS outputs, slew rates are relatively high. However, when VH-VL is relatively small such as for ECL outputs, slew rates are reduced to prevent excessive overshoot.

Abstract: A color subcarrier signal generator for use e.g, in a video converter measures the average error of the horizontal synchronizing signal frequency. The measured error is used as a compensator signal to control a direct digital synthesizer to generate a correct color subcarrier signal. The direct digital frequency synthesizer includes an address generator receiving the error signal and a look up table driven by the address generator.

Abstract: Read errors in data transferred from a remote memory to a buffer memory are detected and corrected by a series of error detection and correction techniques. In the present invention, the transferred data includes user data, a checksum that detects read errors in the user data, row and column syndromes that identifies read errors in the user data, and a Hamming code that identifies read errors in the row and column syndromes. To minimize any performance degradation, a checksum is initially calculated from the user data and compared with the stored checksum. If an error is detected, a Hamming code is calculated from the stored row and column syndromes and compared with the stored Hamming code. Corrections are made, as needed, and then row and column syndromes are calculated from the user data. The calculated row and column syndromes are then compared with the stored row and column syndromes the identify and correct single-bit read errors, and report multiple-bit read errors.

Abstract: There is disclosed a static RAM cell and MOS device for making the cell along with a process for making the types of devices disclosed. The devices is an MOS device built in an isolated island of epitaxial silicon similar to bipolar device isolation islands, and has single level polysilicon with self-aligned silicide coating for source, drain and gate contacts such that no contact windows need be formed inside the isolation island to make contact with the transistor. The static RAM cell formed using this device uses extensions of the polysilicon contacts outside the isolation islands as shared nodes to implement the conventional cross coupling of various gates to drain and source electrodes of the other transistors in the flip flop. Similarly, extensions of various gate, source and drain contact electrodes are used as shared word lines, and shared Vcc and ground contacts.

Abstract: Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

Abstract: There is disclosed a static RAM cell and MOS device for making the cell along with a process for making the types of devices disclosed. The devices is an MOS device built in an isolated island of epitaxial silicon similar to bipolar device isolation islands, and has single level polysilicon with self-aligned silicide coating for source, drain and gate contacts such that no contact windows need be formed inside the isolation island to make contact with the transistor. The static RAM cell formed using this device uses extensions of the polysilicon contacts outside the isolation islands as shared nodes to implement the conventional cross coupling of various gates to drain and source electrodes of the other transistors in the flip flop. Similarly, extensions of various gate, source and drain contact electrodes are used as shared word lines, and shared Vcc and ground contacts.

Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.