Patents Assigned to Faraday Semi, Inc.
  • Patent number: 11855534
    Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 26, 2023
    Assignee: FARADAY SEMI, INC.
    Inventors: Seungbeom Kevin Kim, Jack Walter Cornish, III, Saurabh Anil Jayawant, Parviz Parto
  • Patent number: 11652062
    Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 16, 2023
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 11621230
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 4, 2023
    Assignee: Faraday Semi, Inc.
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 11557962
    Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 17, 2023
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 11069624
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Faraday Semi, Inc.
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 11063516
    Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 13, 2021
    Assignee: Faraday Semi, Inc.
    Inventors: Seungbeom Kevin Kim, Jack Walter Cornish, III, Saurabh Anil Jayawant, Parviz Parto
  • Patent number: 10924011
    Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 16, 2021
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 10504848
    Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 10, 2019
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto