Patents Assigned to FAST SIC SEMICONDUCTOR INCORPORATED
-
Patent number: 11888056Abstract: A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (Wg) which is satisfied the following formula: Wg>Wjfet+2×Lch+2×Lx Lch represents a channel length of channel regions, Wjfet represents a minimum width of JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region.Type: GrantFiled: September 7, 2021Date of Patent: January 30, 2024Assignee: FAST SIC SEMICONDUCTOR INCORPORATEDInventor: Cheng-Tyng Yen
-
Patent number: 11489521Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.Type: GrantFiled: August 10, 2021Date of Patent: November 1, 2022Assignee: FAST SIC SEMICONDUCTOR INCORPORATEDInventors: Cheng-Tyng Yen, Fu-Jen Hsu, Hsiang-Ting Hung
-
Patent number: 11195922Abstract: A silicon carbide semiconductor device includes a drift layer having a first conductivity type and a surface in which an active region is defined; a plurality of first doped regions having a second conductivity and arranged within the active region; a plurality of second doped regions having a second conductivity and arranged within the active region; and a metal layer disposed on the surface of the drift layer and forming a Schottky contact with the drift layer. Each of the first doped regions has a first minimum width and a first area and are spaced from each other by a first minimum spacing Each of the second doped regions has a second minimum width greater than the first minimum width and a second area greater than the first area and are spaced from the first doped region by a second minimum spacing less than the first minimum spacing.Type: GrantFiled: June 4, 2020Date of Patent: December 7, 2021Assignee: FAST SIC SEMICONDUCTOR INCORPORATEDInventor: Cheng-Tyng Yen
-
Patent number: 11190181Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or fed back from the power transistor device; wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.Type: GrantFiled: January 19, 2021Date of Patent: November 30, 2021Assignee: FAST SIC SEMICONDUCTOR INCORPORATEDInventors: Cheng-Tyng Yen, Fu-Jen Hsu, Hsiang-Ting Hung
-
Patent number: 11018228Abstract: A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.Type: GrantFiled: July 15, 2020Date of Patent: May 25, 2021Assignee: FAST SIC SEMICONDUCTOR INCORPORATEDInventor: Cheng-Tyng Yen