Abstract: A memory cell may comprise a field-effect transistor structure comprising a gate structure, the gate structure comprising a floating gate electrode separated from a channel of field-effect transistor structure by a gate isolation; a spontaneously polarizable memory layer, wherein the spontaneously polarizable memory layer covers completely an upper surface of the floating gate electrode and wherein the spontaneously polarizable memory layer covers one or more lateral surfaces of the floating gate electrode; a gate electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the gate electrode to form a capacitive memory structure; and a lever electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the lever electrode to form a lever structure.

Abstract: Disclosed herein are devices, methods, and systems for calibrating a read voltage level for reading memory cells of a memory. The calibration circuit includes a reference cell associated with a predefined programming state of the reference cell. The calibration circuit also includes a read circuit configured to (e.g., until a read state of the reference cell matches the predefined programming state), perform a read operation on the reference cell at a reference read voltage level to obtain a read state of the reference cell and adjust the reference read voltage level to an adjusted reference read voltage level based on a comparison between the read state and the predefined programming state. The read circuit is configured to provide the adjusted reference read voltage level to the memory as the read voltage level for reading the memory cells of the memory.

Abstract: Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.

Abstract: Disclosed herein are devices, methods, and systems for reading a programmed state of a memory element. The method includes setting a bit line to which the memory element is connected to a first voltage and developing to the bit line a compensation voltage different from the first voltage. The method also includes developing a modified sensing voltage to the bit line defined by the compensation voltage and a sensing voltage developed from the memory element and determining the programmed state based on the modified sensing voltage. A complementary memory element may be used to develop the compensation voltage by discharging a complementary plate line, to which the second memory element is connected, to charge a complementary bit line to which the second memory element is connected and by connecting the bit line to the complementary bit line to develop the compensation voltage to the bit line.

Abstract: Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure includes a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

Abstract: Various aspects relate to a memory cell including: a field-effect transistor structure, the field-effect transistor structure including a gate structure to control a current flow in a channel, the gate structure including a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and a capacitive memory structure, the capacitive memory structure including at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein one of the at least two electrodes is in direct physical contact with the floating gate of the field-effect transistor structure, and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.

Abstract: Disclosed herein are devices, methods, and systems for calibrating a sensing capacitance value used by a sensing circuit when reading memory cells of a memory. The calibration circuit includes a calibration cell associated with a predefined programming state of the calibration cell. The calibration circuit also includes a read circuit configured to perform a read operation on the calibration cell that generates a calibration voltage based on the predefined programming state and convert the calibration voltage to a target capacitance value based on the calibration voltage. The read circuit is configured to provide the target capacitance value to the memory as the sensing capacitance for the sensing circuit to use when reading the memory cells of the memory.

Abstract: Disclosed herein are devices, methods, and systems for operating a sense amplifier comprising a plurality of transistors connected in a cascode configuration. The plurality of transistors are configured to sense, in a read operation mode, a switching signal from the state-programmable memory element, and to apply, in a write operation mode, a programming voltage level to the state-programmable memory element. The plurality of transistors are configured to receive a supply voltage at, in the read operation mode, a first supply voltage level that is lower than the programming voltage level and at, in the write operation mode, the programming voltage level, and to operate the sense amplifier in the read operation mode and the write operation mode with no more than a maximum operational voltage level across each of the plurality of transistors that is less than the programming voltage level.

Abstract: Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.

Abstract: A ferroelectric memory circuit (100) includes: a memory cell (102), wherein a memory state (102s) of the memory cell (102) is switchable between a first memory state and a second memory state, the memory cell (102) further configured to output an electrical current (101) in response to receiving a readout voltage (103); and a sense circuit (104) configured to output an output voltage (105) based on the result of integrating the electrical current (101) output by the memory cell (102), wherein the output voltage (105) represents whether the memory state (102s) is the first memory state or the second memory state.

Abstract: Disclosed herein are devices, methods, and systems for reading/writing memory cells of a memory, where the memory cells includes a memory element that is writable to at least three different remanent polarization states. A sensing circuit determines, in a read operation, a stored state of the memory element from among the at least three different remanent polarization states based on a sensed change in a remanent polarization of the memory element caused by an applied read voltage. A biasing circuit applies, in a write operation, apply a bias voltage level across the memory element to (re)write the memory element to the stored state.

Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

Abstract: Various aspects relate to a memory device including: a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks includes a gate electrode layer and one or more electrically insulating layers; one or more channel structures extending through the plurality of gate layer stacks, wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells, wherein each field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells includes: a gate layer portion of a gate layer stack of the plurality of gate layer stacks; a channel portion of a channel structure of the one or more channel structures; a spontaneously-polarizable portion; and a floating gate, wherein the spontaneously-polarizable portion and the floating gate are disposed between the gate layer portion and the channel portion.

Abstract: Various aspects relate to a destructive read out operation to read out a memory state of a remanent polarizable capacitive memory element. The destructive read out operation may include causing a voltage drop sequence over the remanent polarizable capacitive memory element, wherein the voltage drop sequence includes one or more voltage drops of a first polarity and one or more voltage drops of a second polarity opposite the first polarity. In some aspects, the destructive read out operation is configured as a bipolar read out operation to determine the memory state of the remanent polarizable capacitive memory element based on an electrical behavior of the remanent polarizable capacitive memory element during the voltage drop sequence.

Abstract: Disclosed herein is a memory cell arrangement and method thereof for providing a reference read current for reading a plurality of memory cells. The memory cell arrangement includes a plurality of memory cells and one or more reference memory cells. The memory cell arrangement also includes a reference circuit that provides a reference read current for reading one or more of the plurality memory cells, wherein the reference circuit is connected to the one or more reference memory cells to generate the reference read current based on one or more reference currents from the one or more reference memory cells. The memory cell arrangement may also include a shifting circuit connected to the reference circuit, wherein the shifting circuit is configured to shift the reference read current.

Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.

Abstract: Disclosed herein is an adaptive voltage regulator that includes a voltage regulator circuit configured to provide a regulated output voltage at an output node of the adaptive voltage regulator circuit. The adaptive voltage regulator also includes an adaptation circuit coupled to the output node that is configured to adapt a charging characteristic associated with a charging of the output node to a predefined output voltage as a function of a load coupled to the output node. The adaption circuit may be configured to selectively provide additional charging current that charges the output node to the predefined output voltage depending on the load.

Abstract: Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: Various aspects relate to a startup circuit for a bandgap reference circuit, wherein a target voltage value is associated with the bandgap reference circuit, the target voltage value being indicative of a startup condition of the bandgap reference circuit that triggers a stable on-state of the bandgap reference circuit, wherein the startup circuit is configured to: provide a startup voltage at the bandgap reference circuit to trigger a start of an operation of the bandgap reference circuit; receive a feedback voltage, wherein the feedback voltage is representative of a startup condition of the bandgap reference circuit; and either increase the startup voltage at the bandgap reference circuit in the case that a voltage value of the feedback voltage is less than the target voltage value, or stop providing the startup voltage at the bandgap reference circuit in the case that the voltage value of the feedback voltage is equal to or greater than the target voltage value.