Patents Assigned to FICT LIMITED
-
Publication number: 20260182474Abstract: Electrical coupling high in reliability without using an adhesive layer is disclosed by stacking a plurality of laminates (30) including a first insulating substrate (14), a metal layer (18) formed on a first surface (14a) of the first insulating substrate (14) to have a pattern, a second insulating substrate (20 (40)) stacked in a place of the first surface (14a) where the metal layer (18) is not disposed so as to have a same thickness as the metal layer (18), a third insulating substrate (22) stacked on a second surface (14b) at an opposite side to the first surface (14a) of the first insulating substrate (14), and a via (26) formed from a surface at an opposite side to the first insulating substrate (14) side of the third insulating substrate (22) until the via (26) reaches the metal layer (18).Type: ApplicationFiled: January 22, 2024Publication date: June 25, 2026Applicant: FICT LIMITEDInventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai
-
Patent number: 12666546Abstract: A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.Type: GrantFiled: March 1, 2021Date of Patent: June 23, 2026Assignee: FICT LIMITEDInventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano, Takayuki Inaba, Akira Yajima, Shin Hirano, Kota Aoi, Tetsuro Miyagawa
-
Patent number: 12520423Abstract: The present invention addresses the problem of providing a circuit board for which the manufacturing process is short and which has a laminate surface having uniform flatness. As a solution to the problem, this method for manufacturing a circuit board includes: manufacturing a three-layer metal (58) having, on one surface thereof, a first metal layer (26) formed in a pattern shape; manufacturing unit structures (60) each having the first metal layer (26), a cured first insulating base material (22) filled with a cured first conductive paste (32), a second metal layer (28), and a semi-cured second insulating base material (24) filled with a semi-cured second conductive paste (36); joining together the first insulating base material (22) in one unit structure (60) among a plurality of the unit structures with the second insulating base material (24) in another unit structure (60); and layering the plurality of unit structures (60).Type: GrantFiled: February 14, 2022Date of Patent: January 6, 2026Assignee: FICT LIMITEDInventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano
-
Publication number: 20250374420Abstract: A laminated substrate includes multilayer substrates stacked, wherein the multilayer substrates are each provided with a through hole which penetrates the multilayer substrates, an inner wall surface of which is plated, and which is filled with resin, and bonding lands formed on upper and lower surfaces of the through hole and electrically coupled to the through hole, an insulating adhesive layer and a conductive paste via for electrically coupling the bonding lands of the multilayer substrates opposed to each other with a conductive paste with which a through hole formed in the insulating adhesive layer is filled are disposed between the multilayer substrates, and the conductive paste via is disposed at a position different from a position at which the through hole is formed.Type: ApplicationFiled: April 23, 2025Publication date: December 4, 2025Applicant: FICT LIMITEDInventors: Norikazu Ozaki, Tetsurou Miyagawa, Takashi Nakagawa, Naoki Sakai
-
Publication number: 20250365869Abstract: A layered body is manufactured by etching a first foil constituting a three-layer metal foil to form a first metal layer shaped like a pattern, stacking a first insulating layer so as to bury the first metal layer, forming a first via as a plated via, forming a second metal layer shaped like a pattern on the first insulating layer, stacking a second insulating layer so as to bury the second metal layer, removing a second foil and a third foil constituting the three-layer metal foil, stacking a third insulating layer and a resin film on the second insulating layer, and providing a second via as a paste via to the second insulating layer, and a multilayer substrate is obtained by stacking a plurality of layered bodies.Type: ApplicationFiled: May 22, 2025Publication date: November 27, 2025Applicant: FICT LIMITEDInventors: Norikazu Ozaki, Tetsurou Miyagawa, Takashi Nakagawa, Naoki Sakai
-
Publication number: 20250194009Abstract: To shorten a manufacturing process and to decrease an interlayer resistance value to thereby increase an allowable current value are set as problems. As means for solving the problems, in a multilayer substrate (20) which includes a plurality of insulating layers (24) and a plurality of metal layers (12) formed on both surfaces of the insulating layers (24) and patterned, and in which the metal layers (12), (12) are interlayer-coupled to each other with vias, there are included layers which are interlayer-coupled to each other with plated vias (14), and layers which are interlayer-coupled to each other with paste vias (16) filled with a conductive paste.Type: ApplicationFiled: December 9, 2022Publication date: June 12, 2025Applicant: FICT LIMITEDInventors: Kenji Iida, Taiji Sakai, Takayuki Inaba, Takashi Nakagawa
-
Publication number: 20240188216Abstract: The present invention addresses the problem of providing a circuit board for which the manufacturing process is short and which has a laminate surface having uniform flatness. As a solution to the problem, this method for manufacturing a circuit board includes: manufacturing a three-layer metal (58) having, on one surface thereof, a first metal layer (26) formed in a pattern shape; manufacturing unit structures (60) each having the first metal layer (26), a cured first insulating base material (22) filled with a cured first conductive paste (32), a second metal layer (28), and a semi-cured second insulating base material (24) filled with a semi-cured second conductive paste (36); joining together the first insulating base material (22) in one unit structure (60) among a plurality of the unit structures with the second insulating base material (24) in another unit structure (60); and layering the plurality of unit structures (60).Type: ApplicationFiled: February 14, 2022Publication date: June 6, 2024Applicant: FICT LIMITEDInventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano
-
Publication number: 20240147613Abstract: The present invention addresses the problem that, when applying pressure and heat to laminate substrates, to maintain the flatness of the substrates so as not to have the load concentrated in one part, and to prevent the occurrence of resistance value abnormalities by making the electrically conductive layers between terminal parts uniform over the entire substrate.Type: ApplicationFiled: April 14, 2022Publication date: May 2, 2024Applicant: FICT LIMITEDInventors: Takashi Nakagawa, Norikazu Ozaki, Taiji Sakai, Kenji Takano, Kenji Iida
-
Publication number: 20240064907Abstract: An object is to provide a circuit board that includes a built-in semiconductor device and has a configuration that prevents cracking and has excellent reliability in operation over a wide temperature range. As a solution, a circuit board (10A) has a configuration in which a first insulating substrate (1) is laminated on a second insulating substrate (2) while interposing a first adhesive layer (7a), and a semiconductor device (9) is embedded in an embedment portion (1c) formed in the first insulating substrate (1).Type: ApplicationFiled: February 22, 2022Publication date: February 22, 2024Applicant: FICT LIMITEDInventors: Taiji Sakai, Kenji Iida, Norikazu Ozaki, Kenji Takano, Takashi Nakagawa, Takayuki Inaba, Tetsuro Miyagawa, Akira Yajima, Shin Hirano, Kota Aoi, Yoichi Abe, Mio Emura
-
Patent number: 11852866Abstract: An issue is directed to suppressing light interference occurring between a plurality of waveguides and providing waveguides at high densities. Means for solving the issue includes a plurality of cores (104) each configured to allow light to be transmitted therethrough, a clad (106) surrounding the plurality of cores (104) and smaller in refractive index for light than each of the cores (104), and a transmission suppression member (108) located between mutually adjacent two cores out of the plurality of cores (104) and configured to suppress transmission of light leaking from each of the cores.Type: GrantFiled: May 1, 2020Date of Patent: December 26, 2023Assignee: FICT LIMITEDInventors: Toshiki Iwai, Taiji Sakai
-
Publication number: 20230180398Abstract: A circuit board includes a plurality of first insulating base materials and a plurality of second insulating base materials that are alternately laminated, a first metal layer being formed into a pattern shape on a first surface of the first insulating base material, and a second metal layer being formed into a pattern shape on a second surface of the first insulating base material. The first metal layer is formed into a trapezoidal shape that is large in diameter on a first surface side of the first insulating base material. The second metal layer is formed into a trapezoidal shape that is large in diameter on a second surface side of the first insulating base material. The first metal layers and the second metal layers are laminated in such a manner that the trapezoidal shapes are alternately oriented.Type: ApplicationFiled: March 1, 2021Publication date: June 8, 2023Applicant: FICT LIMITEDInventors: Kenji Iida, Norikazu Ozaki, Taiji Sakai, Takashi Nakagawa, Kenji Takano, Takayuki Inaba, Akira Yajima, Shin Hirano, Kota Aoi, Tetsuro Miyagawa