Abstract: A data input buffer includes a switching circuit; a reception circuit that includes a reception response unit and a reference response unit; and a code generating circuit. The data input buffer buffers a reception data signal to generate a buffered data signal, the reception data signal being an analog signal, and the buffered data signal being a digital signal, and a relative magnitude of a reference response conductance with respect to the reception response conductance is sequentially changed according to a sequential change of the calibration code, in the calibration mode.

Abstract: A semiconductor memory device of the disclosure comprises a frequency detection circuit that detects the frequency of an input clock signal generated during a measurement time and generates a frequency confirmation data having the information on the frequency of the input clock signal; a status register that receives the frequency confirmation data and generates 1-st to m-th driving control signals; and a 1-st to an m-th operating circuit. In the semiconductor memory device of the disclosure, the operating state can be changed by detecting a frequency change of an input clock signal without an external mode register setting command. As a result, according to the semiconductor memory device of the disclosure, the time required to change the operating mode is reduced.

Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: A pumping voltage generating circuit can include a control information generating block receiving a pumping enable signal and a refresh sequential signal and generating driving force control information, the driving force control information controlled so that a number of pulses of the refresh sequential signal falling within a target pulse number range is generated during the generation of pulses of the pumping enable signal which have the pumping reference number, a pumping generation block generating a pumping voltage with a total pumping force, the total pumping force depending on the data value of the driving force control information, and a level detection block detecting a level of the pumping voltage and generating the pumping enable signal, the pumping enable signal activated when the level of the pumping voltage is outside a target level range, and deactivated when the level of the pumping voltage falls within the target level range.

Abstract: A bit line pre-charge voltage generating circuit in a semiconductor memory device may reduce current consumption. The bit line pre-charge voltage generating circuit includes a reference voltage generating portion that generates a pull-down reference voltage and a pull-up reference voltage; a comparing portion that generates a pull-up comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-up reference voltage, and generates a pull-down comparison signal by comparing the level of the bit line pre-charge voltage with that of the pull-down reference voltage; a driving portion that includes a pull-up driving element and a pull-down driving element; and an activation overlap reduction portion that generates the pull-up control signal and the pull-down control signal The activation overlap reduction portion can minimize the overlap between the turn-on sections of the pull-up driving element and the pull-down driving element of the driving portion.

Abstract: A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.

Abstract: A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.

Abstract: An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.

Abstract: An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

Abstract: An auto refresh limiting circuit includes an oscillating signal generating part that generates an internal oscillating signal, the internal oscillating signal being a pulse having a period reflecting an internal temperature of a semiconductor memory device; a masking signal generating part that generates a masking signal by using an auto refresh command signal and the internal oscillating signal, the masking signal being deactivated during a pulse of the auto refresh command signal, the pulse of the auto refresh command signal being first generated after the pulse of the internal oscillating signal is generated; and an auto refresh masking part that converts the pulse of the auto refresh command signal into a pulse of an auto refresh driving signal, the conversion of the pulse of the auto refresh driving signal being masked according to the activation of the masking signal.

Abstract: Disclosed herein is a semiconductor memory device for reducing data read time difference between memory banks. In the semiconductor memory device of the disclosure, each of the memory banks has the delay control time controlled based on the distance from data control block or receives the signal according to the read command. Accordingly, the data read time difference is reduced in the semiconductor memory device, and the operation time margin of the data control block is improved.

Abstract: A semiconductor memory device of the disclosure comprises a frequency detection circuit that detects the frequency of an input clock signal generated during a measurement time and generates a frequency confirmation data having the information on the frequency of the input clock signal; a status register that receives the frequency confirmation data and generates 1-st to m-th driving control signals; and a 1-st to an m-th operating circuit. In the semiconductor memory device of the disclosure, the operating state can be changed by detecting a frequency change of an input clock signal without an external mode register setting command. As a result, according to the semiconductor memory device of the disclosure, the time required to change the operating mode is reduced.

Abstract: A data transmission/reception device comprises a data bus; a data transmission circuit that recognizes standard data, receives a transmission data, loads a code data into the data bus, and generates a flag signal; and a data reception circuit that receives the flag signal and the code data transmitted through the data bus, and recovers the code data into a reception data according to the activation of the flag signal. According to the data transmission/reception device of the disclosure, current consumption may be reduced during data transmission.

Abstract: In the semiconductor memory device of the disclosure, a half of the 1-st dummy memory cells of the 1-st dummy memory array and a half of the 2-nd dummy cells of the 2-nd dummy memory array can store data. In the semiconductor memory device of the disclosure, dummy memory cells corresponding to one normal memory array may be used to store data. As a result, according to the semiconductor memory device of the disclosure, the degree of integration may be greatly improved.

Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.

Abstract: A data input buffer includes a switching circuit; a reception circuit that includes a reception response unit and a reference response unit; and a code generating circuit. The data input buffer buffers a reception data signal to generate a buffered data signal, the reception data signal being an analog signal, and the buffered data signal being a digital signal, and a relative magnitude of a reference response conductance with respect to the reception response conductance is sequentially changed according to a sequential change of the calibration code, in the calibration mode.

Abstract: An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.

Abstract: Disclosed herein is a semiconductor memory device for reducing data read time difference between memory banks. In the semiconductor memory device of the disclosure, each of the memory banks has the delay control time controlled based on the distance from data control block or receives the signal according to the read command. Accordingly, the data read time difference is reduced in the semiconductor memory device, and the operation time margin of the data control block is improved.

Abstract: An auto refresh limiting circuit includes an oscillating signal generating part that generates an internal oscillating signal, the internal oscillating signal being a pulse having a period reflecting an internal temperature of a semiconductor memory device; a masking signal generating part that generates a masking signal by using an auto refresh command signal and the internal oscillating signal, the masking signal being deactivated during a pulse of the auto refresh command signal, the pulse of the auto refresh command signal being first generated after the pulse of the internal oscillating signal is generated; and an auto refresh masking part that converts the pulse of the auto refresh command signal into a pulse of an auto refresh driving signal, the conversion of the pulse of the auto refresh driving signal being masked according to the activation of the masking signal.