Abstract: When establishing a virtual connection, a pair of identifiers VPI-VCI of Lp+Lc bits is adopted, and data (Id_Cx) relating to said virtual connection is stored in a table in relation to its identifier pair. At the arrival of each ATM cell whose header includes the identifier pair of one of the virtual connections, the data relating to said virtual connection is read from the table. The table includes p.2m storage areas organized as 2m rows and p columns. The data relating to a virtual connection are stored in an area of the table whose row is labelled by an m-bit index calculated by applying a systematic cyclic code, having a generating polynomial of degree m, to a binary word extracted from a sequence of Lp+Lc bits which consists of the bits of one of the identifiers arranged in order of decreasing significance, followed by the bits of the other identifier arranged in order of increasing significance.

Abstract: The equipment includes two connectors for connection to two respective lines, and a multilayer printed circuit, one region of which supports signal processing components, each of the lines including at least two electrical conductors. The printed circuit incorporates essentially inductive electrical links between the connectors and the components. The printed circuit further incorporates metallizations associated with the two connectors which link them respectively to the conductors of the two lines. These metallizations belong to different layers of the printed circuit and are situated facing one another so as to produce capacitive coupling between the two lines so that a fast electromagnetic disturbance arising on one of the lines is diverted to the other line rather than reaching the signal processing components.

Abstract: An ATM switch includes linewise switching matrices each having m inputs and n outputs (mvn), and a synchronous interconnection network linking incoming lines of the ATM switch to the inputs of the matrices, the outputs of the matrices being linked to respective outgoing lines of the ATM switch. The synchronous interconnection network includes: k successive stages of groupwise elementary synchronous switches each having at least one and at most p groups of m inputs and at least one and at most p groups of m inputs and at least one and at most p groups of m outputs; groups of m lines each linking a group of m outputs of a groupwise elementary synchronous switch to a group of m inputs of a groupwise elementary synchronous switch of the following stage; and groups of m lines each linking a group of m outputs of a groupwise elementary synchronous switch of the last stage to the m inputs of a linewise switching matrix.