Abstract: A transistor comprising a substrate comprising a semiconductor layer; a first electrode on the substrate, the first electrode comprising a bus bar and having first and second first electrode fingers extending therefrom, the fingers being spaced apart to define a receiving channel therebetween; a second electrode on the substrate having a second electrode finger spaced apart from the first electrode and extending along the receiving channel to define a gate region between the fingers, the gate region comprising a curved portion beyond the end of the second electrode finger proximate to the bus bar of the first electrode; a gate electrode extending along the gate region, through the curved gate portion; the substrate further comprising an active layer beneath the gate region, the active layer being adapted to change between on and off states on application of a voltage to the gate electrode; characterised in that the active layer extends beyond the end of the second electrode finger beneath the curved port

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; characterised in that the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A multigate Schottky diode comprising an electrically conducting active semiconductor region; first and second electrically connected metallic contact arms on the active semiconductor region forming ohmic contacts therewith; the ohmic contacts being spaced apart on the active semiconductor region to define a gate receiving channel therebetween. a plurality of electrically connected metallic gate fingers, the metallic gate fingers being in contact with the active semiconductor region to form Schottky junctions, the Schottky junctions being spaced apart on the active semiconductor region and extending at least partially along the gate receiving channel.

Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: A linear antenna switch arm comprising a plurality of field effect transistors connected in series, the drain of each transistor being connected to the source of the next transistor at a join, the end source comprising one of a signal input or output port and the end drain comprising the complementary signal output port or input port; a signal line extending between the input and output ports; at least one of the joins being connected to the signal line at a node by a connection line; the signal line comprising at least one resistor between signal input and output ports; and the connection line comprising at least one resistor.

Abstract: A linear antenna switch arm comprising a field effect transistor comprising a source, a drain and a plurality of gates; a signal line connected between source and drain, the signal line comprising at least one signal line resistor; at least one gate being connected to the signal line by a connection line, the join between connection line and signal line comprising a node; the at least one gate being selected from the plurality of gates such that the adjacent gates on each side of the connected gates are not connected to the signal line.

Abstract: A compound field effect transistor having multiple pinch-off voltages comprising: first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein; an ohmic contact layer on the semiconductor layer; a source and a drain on the ohmic contact layer; at least one gate on the semiconductor layer between source and drain; at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it but the gates having different gate lengths.

Abstract: A method of correcting for pattern run out in a desired pattern in directional deposition or etching comprising the steps of providing a test substrate; providing a stencil of known thickness on the test substrate; providing a stencil pattern extending through the stencil to the test substrate.

Abstract: An electrically conducting track comprising an electrically conducting track layer; a semiconductor substrate; and a dielectric layer sandwiched between track layer and semiconductor substrate; the electrically conducting track further comprising an electrically conducting resistor track between semiconductor substrate and dielectric layer

Abstract: A method of handling a semiconductor wafer from which a plurality of semiconductor devices are to be fabricated during a semiconductor device fabrication process. The method includes the steps of attaching a flexible connected layer to a semiconductor wafer layer mounted on a carrier substrate and separating the wafer layer from the carrier substrate while supported by the flexible connected layer.