Patents Assigned to Firefly DSP LLC
  • Patent number: 10025557
    Abstract: An 8×8 binary digital multiplier reduces the height of partial product columns to be no more than 7 bits high. The six 7-bit high middle columns are each input to a (7:3) counter. An ascending triangle compressor operates on the lesser significant bit columns. A descending triangle compressor operates on the greater significant bit columns. The counter and compressor outputs are combined for a final stage of compression, followed by partial product addition.
    Type: Grant
    Filed: December 5, 2015
    Date of Patent: July 17, 2018
    Assignee: Firefly DSP LLC
    Inventors: Craig Franklin, David Cureton Baker
  • Publication number: 20170161021
    Abstract: An 8×8 binary digital multiplier reduces the height of partial product columns to be no more than 7 bits high. The six 7-bit high middle columns are each input to a (7:3) counter. An ascending triangle compressor operates on the lesser significant bit columns. A descending triangle compressor operates on the greater significant bit columns. The counter and compressor outputs are combined for a final stage of compression, followed by partial product addition.
    Type: Application
    Filed: December 5, 2015
    Publication date: June 8, 2017
    Applicant: Firefly DSP LLC
    Inventors: Craig Franklin, David Cureton Baker