Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.

Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, systems and methods can be configured to receive a market order data packet, wherein the market order data packet comprises order information for a market order to be made at a liquidity venue. The market order data packet comprises a header portion and a payload portion, and the header portion comprises at least a portion of the order information. An order symbol is determined based on order symbol information in the header portion. Risk parameters are retrieved associated with the order symbol. It is determined whether or not a risk threshold is exceeded based on the risk parameters and the order information. A final market order data packet is generated for transmission to the liquidity venue based on the determining whether the risk threshold is exceeded.

Abstract: Systems and methods are disclosed that provide real-time pre-trade risk assessments for multiple parties. In one embodiment, a Programmable Logic Device (PLD) may be embedded within an Automated Trading Systems (ATS) architecture by utilizing the Intel socket G or the PCIe interface to provide pre-trade risk functionality. The system may also provide a method for interacting with the ATS DRAM or L1 cache to provide faster access to orders in ATS memory for PLDs. The system may use the Quick Path Interconnect between an embedded processor and a PLD to transfer memory maps. The system may also add additional libraries to an ATS processor to accelerate the transfer or memory maps to a PLD. The system also may use system interrupts to cancel erroneous orders within an ATS processor from a PLD housed within the same physical architecture.