Abstract: A computer system having plural nodes interconnected by a common broadcast bus. Each node has memory and at least one node has a processor. The system has a dynamically configurable memory which may be located within the system address space of a distributed system architecture including memory within each node having a processor and the memory resident within other nodes. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. Memory located anywhere in the distributed system architecture may be partitioned dynamically and accessed on a local basis by programming the partition tables, stored in partitioning RAMs.
Type:
Grant
Filed:
December 15, 1988
Date of Patent:
May 26, 1992
Assignee:
Flashpoint Computer Corporation
Inventors:
Osey C. Parrish, Robert E. Peiffer, Jr., James H. Thomas, Edwin J. Hilpert, Jr.