Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply.

Abstract: Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventional sensing scheme.

Abstract: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

Abstract: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

Abstract: A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vcc to, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than Vcc. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage).

Abstract: Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.