Abstract: Scalable Logic Gate Non-Volatile Memory (LGNVM) NOR-type arrays fabricated by the standard CMOS logic technologies have been applied for the embedded flash solutions in digital circuitries. To significantly reduce the memory array sizes from the previous fabrications, we have applied the topological regularity of memory cells in the arrays and a self-aligned etch process step to eliminate the gate end-caps in the memory areas. Without scarifying the memory array yields, the minimal unit cell size of 12 F2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.

Abstract: A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the device channel have been applied to advanced DRAM process nodes. The same etching process of the recess channel MOSFET device is applied to form the recess channel semiconductor NVM device. The tunneling oxides are grown on silicon surface after the recess channel hole etching process. The storing material is deposited into the recess channel holes with coupling dielectrics on top of the storing material. The gate material is then deposited and etched to form the control gate. Owing to the recess channel embedded below the silicon substrate, the scaling challenges such as gate channel length, floating gate interference, high aspect ratio for gate stack etching, and the mechanical stability of gate formation for the semiconductor NVM device can be significantly reduced.

Abstract: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Abstract: A Dynamic Random Access Memory (DRAM) cell and a semiconductor Non-Volatile Memory (NVM) cell are incorporated into a single Non-Volatile Dynamic Random Access Memory (NVDRAM) cell. The NVDRAM cell is operated as the conventional DRAM cell for read, write, and refreshment on dynamic memory applications. Meanwhile the datum in the NVM cells can be directly loaded into the correspondent DRAM cells in the NVDRAM cell array without applying intermediate data amplification and buffering leading to high speed non-volatile data access. The datum in DRAM cells can be also stored back to the correspondent semiconductor NVM cells in the NVDRAM cells for the datum required for non-volatile data storage. The NVDRAM of the invention can provide both fast read/write function for dynamic memory and non-volatile memory storage in one unit memory cell.

Abstract: An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating with no voltage bias to prevent applied electrical fields toward the source electrode. The drain electrode of the N-channel semiconductor NVM is reversely biased with a positive voltage VDB relative to the substrate to facilitate the valence band electrons in the P-type substrate to tunnel to the conducting band of the N-type drain electrode. A positive high gate voltage pulse is then applied to the gate electrode of the N-channel semiconductor NVM to collect the surface energetic electrons toward the charge storage material.

Abstract: Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (VDD and VSS) to the input nodes of the pair of complementary SGLNVM devices, the output node of the pair of complementary SGLNVM devices outputs digital signals according to its configuration. The NV-LUT outputs digital signals from a plurality of pairs of complementary SGLNVM devices through a digital switching multiplexer. The NV-LUT is a good substitution for SRAM based LUT commonly used in Field Programmable Gate Array (FPGA).

Abstract: An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC).

Abstract: Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.

Abstract: Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

Abstract: A rechargeable battery is disclosed. The rechargeable battery of the invention includes a high density capacitor and an integrated circuit. The high density capacitor is connected to a ground terminal and a first node carrying a first voltage. The integrated circuit includes a band gap circuit, a first detecting unit, a voltage divider, a second detecting unit and at least one low dropout voltage regulator. The band gap circuit generates a band gap voltage according to the first voltage. The first detecting unit measures the first voltage and determines whether to apply an input charging voltage to the high density capacitor. The voltage divider is connected in parallel with the high density capacitor and has a second node carrying a second voltage. The second detecting unit measures the second voltage according to the band gap voltage and determines whether to connect a third node to the first node.

Abstract: Structures and methods of converting Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bit information are disclosed. In MLC NVM system, multi-bit information stored in NVM cell is represented by the states of NVM cell threshold voltage levels. In this disclosure, “P” states of NVM cell threshold voltage levels are divided into “N” groups of threshold voltage levels. Each group contains “M” states of multiple threshold voltage levels of NVM cells, where P=N×M. The “M” states of NVM cell threshold voltage levels in each group are sensed and resolved by applying one correspondent gate voltage to the group. By applying “N” multiple gate voltages, the whole “P” states of NVM cell threshold voltage levels can be sensed and efficiently converted into storing bits in the MLC NVM cells.

Abstract: A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell.

Abstract: Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.

Abstract: Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a ‘gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.

Abstract: Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

Abstract: Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply.