Abstract: An integrated circuit includes a plurality of logic tiles, wherein each logic tile is configurable to connect with at least one adjacent logic tile; a first logic tile includes: (i) an input clock path which is associated with an edge and to receive a tile input clock signal, (ii) a plurality of output clock paths, each output clock path is associated with an edge of the tile and includes at least one u-turn circuit to: (a) receive a tile clock signal having a predetermined skew relative to the tile input clock signal and (b) output a tile clock signal having a predetermined skew relative to a tile output clock signal, (iii) a tile clock generation path which includes a plurality of the u-turn circuits to generate a tile clock based on the tile clock signals, and (iv) programmable logic circuitry to perform operations using the tile clock.

Abstract: An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.