Abstract: Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

Abstract: Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.