Abstract: Systems, methods, and apparatuses are provided that enable streaming of ATM cells between a transmit/receive data processing application and a transmission convergence function. Data to be segmented into an ATM cell is received at a SAR engine, and provided to a transmission convergence function, with the first cells transmitted to the transmission convergence function before the SAR function receives an end-of-packet indication from the optimization engine. Data received at a transmission convergence function is placed in a received packet queue at the SAR function, with packets provided to an application after a start-of-packet indication is received, and before an end-of-packet indication is received, at the SAR function.

Abstract: A physical layer device distributes a high-speed packet data stream to multiple lower-speed physical channels, and reverses the process to receive a high-speed packet data stream that has been distributed across multiple lower-speed physical channels. The packet data is distributed by removing interpacket gap characters from between packets and using a different control character to delineate packets. Interpacket gap characters can then be used to delineate equal-length frames distributed to each of the multiple physical channels. Each frame consists of a concatenation of fixed-size blocks of packet data. By selecting a frame size larger than the average packet size, overhead on the multiple physical channels can actually be lower than the overhead on the single high-speed channel, allowing the aggregation to achieve line rate operation at the high-speed rate.

Abstract: In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Several lanes are coded separately in this manner, and then multiplexed on a common channel. Alignment sequences in the control character sequences, as well as scrambler seeds, are set to avoid synchronization of patterns generated among all lanes, which would tend to confuse a receiving serdes and/or phase-locked loop that recovers timing from the multiplexed scrambled signals.

Abstract: Methods of designing a backplane, a backplane, and a packet switch using such a backplane are disclosed. The backplane comprises communication channels that connect each of a set of first card slots to each of a set of second card slots. Instead of forcing the backplane to route the communication channels to match a preset card configuration, the backplane communication channels are routed so as to reduce crosstalk and attenuation on at least the most difficult routing pairs. The cards perform logical translation of their backplane traffic to conform to the physical pin assignment for the particular card slot in which they are inserted. Other embodiments are also described and claimed.

Abstract: Traffic engineering using a label-switching protocol is enhanced for label-switched paths that traverse a logical link that is an aggregation of component links. In one embodiment, a label edge router is provided with information regarding the bandwidth capabilities and loading of the component links of a LAG. The label edge router is then allowed to set up paths that traverse a specific component link of a LAG, and reserve bandwidth on such a component link. Other traffic may continue to be distributed across the LAG membership.

Abstract: Plated through holes pass through clearances in a ground plane of a circuit board. A conductive collar/spoke arrangement is constructed on the ground plane adjacent the clearance, to provide an inductive component to the coupling between a plated through hole and the ground plane. The inductive component impedes the transfer of high-frequency noise between the through hole and the ground plane. Other embodiments are also described and claimed.

Abstract: In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Advantageously, the sender of the scrambled data can be changed during the control character sequence. The hybrid backplane coding scheme can be designed such that the power spectral density of scrambled data and control character sequences are similar, which permits good performance with high-speed electrical differential receivers. Other embodiments are described and claimed.

Abstract: A virtual link aggregation-capable service provider network and network edge device are described. In at least one embodiment, the service provider edge devices forward packets across the service provider network between pairs of customer ports, including link aggregation packets that would ordinarily be consumed by the edge device. This allows the customer to bridge a link aggregation across a service provider network. Other embodiments are also described and claimed.

Abstract: A method is disclosed for preventing an unstable BGP Peer from repeatedly initializing unstable BGP connections. In one embodiment, BGP speakers are penalized for causing errors that result in BGP restarts. When a speaker accumulates enough penalty points, its peer notifies it that it has been dampened (prevented from establishing a BGP connection). A memory decay function allows the speaker to automatically attempt a new connection once a given amount of time has passed. The method allows at least two, and possibly more, BGP speakers to avoid network and processor costs from servicing unstable BGP peerings.

Abstract: Apparatus and methods for epoch retransmission in a packet network device are described. In at least one embodiment, epoch receivers check received epoch data for errors. When an error is detected, a receiver is allowed to request that the entire epoch be retransmitted. All epoch senders retain transmitted epoch data until the time for requesting a retransmission of that data is past. If retransmission is requested by any receiver, the epoch is “replayed.” This approach mitigates the problem of dropping multiple packets (bundled in a large epoch) due to an intraswitch error with the epoch. Other embodiments are also described and claimed.

Abstract: Transparent point-to-point connectivity is provided between an incoming interface on an ingress node and an outgoing interface on an egress node in a network. An address associated with the egress node is circulated to the nodes in the network and a next hop address toward the egress node address is determined at each node. A label value is circulated along with the egress node address to the nodes. Examples of label values can include VLAN Ids or Multi-protocol Label Switching (MPLS) labels. If data is received having the label value, the node receiving the data identifies the next hop address associated with that label value and transfers the data to the next hop associated with the identified next hop address.

Abstract: An accelerated boot process for a multiprocessor system and system components for use with the process are disclosed. Each processor caches at least one compressed system image in local nonvolatile memory. The processors boot concurrently, each using a local image. After a master processor is booted, the other processors verify with the master that each has booted a correct image version. Various redundancy and fallback features are described, which guarantee that all cards can boot and operate even if the preferred local system image contains a defect.

Abstract: A dynamic multiple spanning tree protocol is described. In at least one embodiment, this protocol allows for the dynamic creation and destruction of mappings between traffic attributes and spanning tree instances with the spanning tree region. These mappings are determined based on the observation of events in the spanning tree, such as the appearance of a significant traffic stream, not mapped to any spanning tree instance, at an edge port of the region. Other embodiments are also described and claimed.

Abstract: A distributed spanning tree protocol is implemented on a modular packet switch. At least some port-specific spanning tree functionality, for instance a port receive state machine and/or a port transmit state machine, operates on a processor on a line port module. At least some bridge-specific spanning tree functionality operates on a processor on a management or control module. When the spanning tree is stable, the line port module processor handles routine spanning tree “hello” messages without having to involve the control module processor. This arrangement allows the switch to handle large and/or multiple spanning trees and large numbers of bridged ports without overloading the control module processor with routine spanning tree module communications.

Abstract: A method and apparatus for receiving clocked data signals such as SPI-4.2 data signals is described. In one embodiment, each data signal lane is deskewed with respect to the clock by oversampling the signal on that lane, and considering multiple versions of a data sequence at different temporal offsets to the clock for correct reception of a training sequence. One of the temporal offsets is subsequently selected to provide the received bit sequence for that lane. Other embodiments are described and claimed.

Abstract: A networking system including virtually addressed devices is described. A network device has one or more virtual addresses assigned to its loopback interface. Once so assigned and the loopback interface enabled, data and commands directed to any of the assigned virtual addresses is sent through the device's protocol stack. The device is then structured to act on the data and commands destined for the virtual address.

Abstract: Multiple comparators compare the enable and priority values for multiple inputs and select a winner from one of the inputs. Multiple comparator stages each include one or more of the comparators. Each comparator stage selects winners from the outputs of a preceding comparator stage. The overall winners are those inputs that are winners in each comparator stage. If there are multiple overall winners, a second arbitration is preformed to identify an ultimate winner.

Abstract: A packet inspection apparatus is described. In one embodiment, the packet inspection apparatus comprises a packet inspection module to compare data from one or more packets of multiple packets with one or more signatures to identify a match, and at least one network interface modules coupled to the packet inspection module. The network interface module has two ports for forwarding full-duplex traffic therebetween, where the traffic includes packets. The one or more network interface modules forward the packets to the packet inspection module and blocks one or more packets in response to an indication from the packet inspection module.

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.