Abstract: A computer is provided that has a plurality of insertion cards that are interconnected via a bus. One insertion card includes a local processing unit and a first intermediate memory for intermediate storage of messages intended for the local processing unit, and a second intermediate memory for intermediate storage of messages originating from the local processing unit. A third intermediate memory and a fourth intermediate memory are provided for free message locations that are intended for or originate from the local processing unit. The second and the third intermediate memories are each provided with a respective intermediate memory extension in a local memory of the local processing unit.

Abstract: Disclosed is a computer having a plurality of adapter cards which are insertable in adjacent bus segments, which are routed interleaved in the middle of a backplane and standard connectors are provided with connections alternating between the two bus segments. Both bus segments are connected to each other by a bridge circuit which includes at least one CPU adapter card. The invention is characterized by two bridge members each of which has an I/O unit and a CPU unit which are fixedly connected to each other. They are insertable in the bus segments with the I/O units inserted in one bus segment and the CPU units inserted in the other bus segment.

Abstract: A computer having a plurality of plug-in modules is provided with a holding circuit for transmitting an interrupt signal over an interrupt signal line. The holding circuit conducts the interrupt signal in the appropriate manner regardless of whether or not a given module is plugged in. At the same time it ensures that a plugged-in module responds to the interrupt signal in the appropriate manner.

Abstract: A computer constructed in accordance with the invention includes at least one transmitting and two receiving structural components. At least the receiving structural components are connected with one another by connecting lines that are arranged in parallel with one another. These connecting lines include data lines and also addressing lines by which each of at least the receiving structural components can be uniquely addressed. When addressed by the appropriate addressing signal, the respective receiving structural component reads the data that is then present at the data lines. A decoder is provided in the transmitting structural component. This decoder is operative for decoding the addressing lines which respectively address the receiving structural components in such a manner that simultaneous addressing of several structural components is possible. The receiving structural components are connected with one another and with the transmitting structural component by a common feedback line.