Patents Assigned to Force Mos Technology Co., Ltd.
  • Patent number: 11450708
    Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: September 20, 2022
    Assignees: MACROBLOCK, INC., FORCE MOS TECHNOLOGY CO., LTD.
    Inventors: Kao-Way Tu, Yuan-Shun Chang, Li-Chang Yang, Yi-Sheng Lin
  • Patent number: 11056488
    Abstract: A metal-oxide-semiconductor (MOS) device comprising a heavily doped substrate, an epitaxial layer, an open, a plurality of MOS units, and a metal pattern layer is provided. The epitaxial layer is formed on the heavily doped substrate. The open is defined in the epitaxial layer to expose the heavily doped substrate. The MOS units are formed on the epitaxial layer. The metal pattern layer comprises a source metal pattern, a gate metal pattern, and a drain metal pattern. The source metal pattern and the gate metal pattern are formed on the epitaxial layer. The drain metal pattern fills in the open and is extended from the heavily doped substrate upward to above the epitaxial layer.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: July 6, 2021
    Assignee: Force MOS Technology Co., Ltd.
    Inventors: Kao-Way Tu, Yuan-Shun Chang
  • Publication number: 20210126047
    Abstract: A metal-oxide semiconductor module includes multiple metal-oxide semiconductor components separated from one another by at least one first trench. Each of the metal-oxide semiconductor components includes a heavily doped semiconductor layer which includes a drain region, an epitaxial layer which is formed with an indentation such that the drain region is partially exposed from the epitaxial layer, and a metallic patterned contact unit. The epitaxial layer also includes a source region and a gate region that are spaced-apart formed therein. The metallic patterned contact unit includes source, gate, and drain patterned contacts which are electrically connected to the source, gate, and drain regions, respectively. A light-emitting diode display device including the metal-oxide semiconductor module is also disclosed.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Applicants: MACROBLOCK, INC., FORCE MOS TECHNOLOGY CO., LTD.
    Inventors: Kao-Way Tu, Yuan-Shun Chang, Li-Chang Yang, Yi-Sheng Lin
  • Patent number: 10700175
    Abstract: A fabricating method of a shielded gate MOSFET is provided, includes the steps of forming a semiconductor substrate having a trench, forming a sacrifice oxide layer in the trench, the sacrifice oxide layer covering a side wall of the trench, forming a source polycrystalline silicon region in the trench, forming an insulation oxide layer above the source polycrystalline silicon region to have the source polycrystalline silicon region fully enclosed by the sacrifice oxide layer and the insulation oxide layer, depositing polycrystalline silicon into the trench and carrying out a back etching to control a thickness of the insulation oxide layer above the source polycrystalline silicon region, forming a gate oxide layer in the trench, the gate oxide layer covering the side wall of the trench, forming a gate polycrystalline silicon region in the trench, and forming a body layer and a heavily doped region around the trench in an ion implantation manner.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: June 30, 2020
    Assignee: Force MOS Technology Co., Ltd.
    Inventors: Kao-Way Tu, Po-An Tsai, Huan-Chung Weng
  • Patent number: 9953969
    Abstract: A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 24, 2018
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9530867
    Abstract: A method for manufacturing a super junction trench MOSFET by growing a first epitaxial layer of a first conductivity type upon a heavily doped substrate layer of a first conductivity type; forming a deep trench mask covering a top surface of the first epitaxial layer; applying a trench mask to form a deep trench extending into the substrate layer by successively dry oxide etch and dry silicon etch; and carrying out angle ion implantations of the first conductivity type dopant and driving-in to form a first type column regions with column shape within the first epitaxial layer; and carrying out angle ion implantations of a second conductivity type dopant and diffusion to form a second type column regions with column shape adjacent to sidewalls of the deep trench, in parallel with and surrounding the first type column regions; and removing the hard mask.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 27, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9530882
    Abstract: A trench MOSFET with diffused drift region and closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 27, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9412810
    Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 9, 2016
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9337328
    Abstract: A super-junction trench MOSFET with closed cell layout is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell. Trenched source-body contacts are disposed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20160104702
    Abstract: A super-junction trench MOSFET integrated with embedded trench Schottky rectifier is disclosed for soft reverse recovery operation. The embedded trench Schottky rectifier can be integrated in a same unit cell with the super-junction trench MOSFET.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: FU-YUAN HSIEH
  • Patent number: 9293527
    Abstract: A super-junction trench MOSFET is disclosed by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. A buffer poly-silicon layer is deposited above the buried void for stress release to prevent wafer crack and silicon defects.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 22, 2016
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20150221733
    Abstract: A trench MOSFET structure having self-aligned features for mask saving and on-resistance reduction is disclosed, wherein source regions are formed by performing source Ion Implantation through contact holes of a contact interlayer in the middle of adjacent terrace trenched gates, and further source diffusion. Both the contact holes and source regions are self-aligned to the terrace trenched gates.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Patent number: 9099320
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 4, 2015
    Assignee: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9018701
    Abstract: A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8999789
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 9000515
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20150076594
    Abstract: A super junction structure having implanted column regions surrounding an N epitaxial layer in a deep trench is disclosed to overcome charge imbalance problem and to further reduce Rds. The inventive super junction can be used for MOSFET and Schottky rectifier.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: FU-YUAN HSIEH
  • Patent number: 8907415
    Abstract: A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20140346593
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Force Mos Technology Co., Ltd.
    Inventor: FU-YUAN HSIEH
  • Patent number: 8889513
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 18, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh