Patents Assigned to Force Mos Technology Co., Ltd.
  • TRENCH MOSFET WITH SUPER PINCH-OFF REGIONS
    Publication number: 20120080748
    Abstract: A trench MOSFET with short channel length and super pinch-off regions is disclosed, wherein the super pinch-off regions are implemented by forming at least two type pinch-off regions for punch-through prevention: a first type pinch-off region with a wide mesa width generated between lower portion of two adjacent trenched gates and below an anti-punch through region surrounding bottom of a trenched source-body contact filled with metal plug; a second type pinch-off region with a narrow mesa width generated below a body region and between upper portion of one trenched gate and the anti-punch-through region along sidewall of the trenched source-body contact.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Power semiconductor devices integrated with clamp diodes having separated gate metal pads to avoid breakdown voltage degradation
    Patent number: 8148773
    Abstract: A structure of power semiconductor device integrated with clamp diodes having separated gate metal pad is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 3, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND TRENCHED CONTACTS
    Publication number: 20120074489
    Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 29, 2012
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND SPLIT GATE ELECTRODES
    Publication number: 20120061754
    Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide and split gate electrodes is disclosed. The inventive structure can apply additional freedom for better optimization of device performance and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Application
    Filed: November 23, 2011
    Publication date: March 15, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • METHOD FOR MANUFACTURING A SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND TRENCHED CONTACTS
    Publication number: 20120064684
    Abstract: A method of manufacturing a super junction semiconductor device having resurf stepped oxide structure is disclosed by providing semiconductor silicon layer having trenches and mesas. A plurality of first doped column regions of a second conductivity type in parallel surrounded with second doped column regions of a first conductivity type adjacent to sidewalls of the trenches are formed by angle ion implantations into a plurality of mesas through opening regions in a block layer covering both the mesas and a termination area.
    Type: Application
    Filed: November 18, 2011
    Publication date: March 15, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • LDMOS with double LDD and trenched drain
    Patent number: 8120106
    Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: February 21, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET HAVING FLOATING DUMMY CELLS FOR AVALANCHE IMPROVEMENT
    Publication number: 20120032261
    Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Method for making a trench MOSFET with shallow trench structures
    Patent number: 8105903
    Abstract: A method for making a trench MOSFET with shallow trench structures with a thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird's beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: January 31, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • METHOD OF MANUFACTURING TRENCH MOSFET STRUCTURES USING THREE MASKS PROCESS
    Publication number: 20120021580
    Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.
    Type: Application
    Filed: September 29, 2011
    Publication date: January 26, 2012
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • MSD integrated circuits with shallow trench
    Patent number: 8101993
    Abstract: A trench MOSFET device with embedded Schottky rectifier, gate-drain and gate-source diodes on single chip is formed with shallow trench structure to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes. More particularly, gate charge of the present semiconductor device is reduced due to the shallow trench surrounded by an additional N doped area around the bottom while keeping Rds low enough and at the same time, maintaining BV at a certain level.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 24, 2012
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION
    Publication number: 20110316075
    Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.
    Type: Application
    Filed: June 29, 2011
    Publication date: December 29, 2011
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Avalanche capability improvement in power semiconductor devices having dummy cells around edge of active area
    Patent number: 8072000
    Abstract: A structure of power semiconductor device having dummy cells around edge of active area is disclosed. The UIS test result of said improved structure shows that failed site after UIS test randomly located in active area which means avalanche capability of the semiconductor power device is enhanced by implementation of the dummy cells.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: December 6, 2011
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Super-junction trench MOSFET with resurf step oxide and the method to make the same
    Patent number: 8067800
    Abstract: A super-junction trench MOSFET with Resurf Stepped Oxide is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 29, 2011
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • LOW Qgd TRENCH MOSFET INTEGRATED WITH SCHOTTKY RECTIFIER
    Publication number: 20110284954
    Abstract: An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Trench MOSFET structures using three masks process
    Patent number: 8058685
    Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 15, 2011
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • SEMICONDUCTOR DEVICES WITH GATE-SOURCE ESD DIODE AND GATE-DRAIN CLAMP DIODE
    Publication number: 20110266593
    Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 3, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan Hsieh
  • SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION
    Publication number: 20110254071
    Abstract: A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan Hsieh
  • SHIELDED TRENCH MOSFET WITH MULTIPLE TRENCHED FLOATING GATES AS TERMINATION
    Publication number: 20110254086
    Abstract: A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • TRENCH MOSFET WITH TRENCHED FLOATING GATES IN TERMINATION
    Publication number: 20110254070
    Abstract: A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan HSIEH
  • Trench mosfet with body region having concave-arc shape
    Publication number: 20110248340
    Abstract: A trench Metal Oxide Semiconductor Field Effect Transistor with improved body region structures is disclosed. By forming the inventive body region structures with concave-arc shape with respect to epitaxial layer, a wider interfaced area between the body region and the epitaxial layer is achieved, thus increasing capacitance between drain and source Cds. Moreover, the invention further comprises a Cds enhancement doped region interfaced with said body region having higher doping concentration than the epitaxial layer to further enhancing Cds without significantly impact breakdown voltage.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Applicant: FORCE MOS TECHNOLOGY CO. LTD.
    Inventor: Fu-Yuan Hsieh