Patents Assigned to Force-MOS Technology Corp.
  • Patent number: 8022471
    Abstract: A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 20, 2011
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7863685
    Abstract: A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7812409
    Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 12, 2010
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7800185
    Abstract: A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the semiconductor power device further includes a source region disposed only in regions near the trenched gates in the closed N-channel MOSFET cells and away from regions near the wider trenched gate whereby a device ruggedness is improved. The source region is further disposed at a distance away from a corner or an edge of the semiconductor power device and away from a termination area. The semiconductor device further includes multiple trenched rings disposed in a termination area opposite the active area and the trenched rings having a floating voltage. The closed N-channel MOSFET cells are further supported on a red phosphorous substrate.
    Type: Grant
    Filed: January 28, 2007
    Date of Patent: September 21, 2010
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7633121
    Abstract: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 15, 2009
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh