Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract: A packet network device such as a network switch includes a number of functional cards or chassis modules at least some of which are connected to both an electrical backplane and a wireless backplane. The electrical backplane provides data plane signal paths and the wireless backplane provides control plane signal paths.

Abstract: A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

Abstract: A packet network device such as a network switch includes a number of functional cards or chassis modules at least some of which are connected to both an electrical backplane and a wireless backplane. The electrical backplane provides data plane signal paths and the wireless backplane provides control plane signal paths.

Abstract: A network device such as a router or a switch is comprised of a control module and a plurality of physical line cards. The control module includes a control processor virtual machine, a plurality of route processing virtual machines and one or more instances of a line card virtual machine. The line card virtual machine operates to receive routing information base update information, to modify the routing information base according to the update information and to update each instance of a plurality of forwarding information bases included on each of the physical line cards.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A network packet is segmented for transfer through a switch fabric. The last segment of the packet is allowed to exceed the maximum size of previous segments so as to increase the switch fabric utilization. Other features are also provided.

Abstract: A BGP capable packet network device is located at the boundary of an autonomous network and in communication with a peer BGP capable packet network device in a neighboring autonomous network. The BGP capable packet network device is comprised of one or more line cards for receiving and, processing and sending packets of information, and for receiving and forwarding routing update information to a route processor comprising the packet network device. The route processor runs a border gateway protocol which is configured with one or more policies that operate to filter the routing update information received from the line card. The routing update information filter is comprised of at least one variable length path attribute and the filter operates such that it only applies the variable length path attribute one time to the routing update information.

Abstract: A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract: A local network, such as a data center, includes a plurality of servers each of which are linked to a network switch. Some of the plurality of servers are network virtualization capable and some are not. The network virtualization capable servers include functionality that encapsulates a data frame, generated by one network virtualization servers that is to be sent to another network virtualization capable server, with a network virtualization identity. In the event that a network virtualization server generates a data frame for transmission to a server that is not capable of network virtualization, the network virtualization capable server does not encapsulate the data frame with the network virtualization identity.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A network switch suitable for receiving packets of information from and the packets of information to a communications network includes a plurality of physical ports, packet processing functionality and memory. The packet processing functionality operates on information stored in memory to determine the LAG, from among two or more LAGs, over which a packet received by the switch should be correctly forwarded. The switch memory stores a plurality of LAG tables, each one of which can include one or more entries comprising a physical port number and a packet parameter that are used by the packet processing functionality to determinately identify the correct LAG over which to forward a packet.

Abstract: A stacked switch includes two or more individual network switches connected to each other in a ring or daisy chain topology over stacking links, and at least one port on two or more of the individual switches comprising the stacked switch is a member of a LAG configured on the stacked switch. Each of the individual switches comprising the stacked switch include control plane and data plane functionality that operates to maintain switching tables and to process network data ingressing to the switch to determine how to forward the network data through the switch to an egress point. The control functionality included in each of the switches comprising the stacked switch also includes an enhanced ECMP functionality that operates to optimize the use of stacking link bandwidth on the stacking links connecting the two or more individual switches to each other.

Abstract: A LAN includes a CORE switch linked to some number of TOR switches, and each of the TOR switches are linked directly to some number of host devices. Each of the switches in the LAN operate to process and transmit data frames they receive from neighboring LAN devices. Each TOR switch in the LAN builds and maintains a layer-2 forwarding table that is comprised of MAC address information learned from frames they receive from neighboring LAN devices. Selected ports/VLANs on some or all of the TOR devices are designated to be CORE/switch facing ports (CFP) or host facing ports (HFP). Each of the CFPs are configured to only learn the MAC address in unicast frames it receives and each of the HFPs can be configured to learn the MAC address of both unicast and multicast data frames provided the destination MAC address included in the unicast frame is known.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: Two network switches are configured in a stacked relationship to each other and include link aggregation sub-layer functionality. Switching tables are programmed on each switch with information used to forward packets ingressing to them over a redundant LAG that is identified in the switching table by a port that is a member of the redundant LAG.

Abstract: A packet network system, such as an autonomous system, includes a plurality of packet network devices some of which are edge routers and some of which are core routers. Each of the edge and core routers include functionality that operates to receive network traffic, process the traffic as needed and to forward the traffic to its destination. Additionally, each router includes a traffic distribution function that operates to calculate path bandwidths for all of the paths over which the traffic can be forwarding through the system and to use the volume of traffic ingressing to the system, link utilization information and the calculated path bandwidth to redistribute the traffic in the system such that traffic loss in the system in minimized.

Abstract: A virtual chassis includes two or more physical chassis and operates as a single, logical device. Each of the two or more physical chassis include two route processor modules (RPM) and each RPM is assigned a first and a second role within the virtual chassis. The first role is a physical chassis level role and the second role is a virtual chassis level role. The RPMs operate in coordination such that the failure of any one of the RPMs results in one or more other RPMs taking over the first and second roles of the failed RPM.