Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.

Abstract: A mechanism for effectively preventing damage to a GaAs-resident semiconductor device directs electrostatic charge buildup to a neutralizing source of reference potential by means of a parasitic bypass Schottky circuit that is effectively invisible to normal input signals, but which otherwise provides a current sink discharge path for the unwanted electrostatic charge. The mechanism employs one or more parasitic Schottky diodes formed as a result of the deposition of input/power supply metal on the surface of a semi-insulating GaAs substrate, coupled in series with low resisitivity regions between the input metal and respective power supply terminals.

Abstract: An output pad driver circuit for an integrated circuit chip architecture incorporates a controllably switched current mirror circuit in the circuit path between an output pad driver input terminal to which a digital signal produced by the signal processing circuitry of the chip is applied and an output terminal from which an output signal produced by the output pad is produced. The controllably switched current mirror circuit is coupled to a reference current terminal to which a source of reference current is applied. Coupled between the input terminal and the current mirror circuit is a first switching transistor which controllably causes the controllably switched current mirror circuit to apply a controlled current to the output terminal in response to a prescribed change in the logic level of an input signal that is applied to the input terminal.