Abstract: A data capture system (1) has modular amplifier circuits (10) connected to modular capture circuits (11) within a rotor 2. Each capture circuit (11) has an FPGA (26) operation according to low-frequency and high-frequency state machines (M1, M2) to control ADCs (25) and upload from memories (30) to a host (15) During sampling, each FPGA (26) runs through a ready mode, a sampling mode, and again a ready mode according to a host command.
Type:
Grant
Filed:
May 23, 2000
Date of Patent:
December 30, 2003
Assignee:
Forfàs
Inventors:
Martin J Leahy, Catherine Byrne, Stephen Clothier, Gerard O'Regan, Philip Samways, Jeffrey Punch, Mark Davies