Abstract: Systems and methods for depositing a plurality of droplets in a three-dimensional array are disclosed. The array can comprise a first type of droplets disposed to form a support structure and a second type of droplets forming a conductive seed layer on the support structure. A structure material can be electrodeposited onto the seed layer to create a three-dimensional structure.
Type:
Application
Filed:
December 21, 2005
Publication date:
June 21, 2007
Applicant:
FORMFACTOR, INC.
Inventors:
Gaetan Mathieu, Treliant Fang, Eric Hobbs
Abstract: A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, and unpluggable using pins, enabling movement over a range of positions.
Type:
Grant
Filed:
June 15, 2004
Date of Patent:
June 12, 2007
Assignee:
FormFactor, Inc.
Inventors:
Benjamin N. Eldridge, Barbara Vasquez, Makarand S. Shinde, Gaetan L. Mathieu, A. Nicholas Sporck
Abstract: A probe card assembly can comprise a probe head assembly and a wiring substrate. The probe head assembly can comprise a plurality of probes disposed to contact an electronic device disposed on a holder in a test housing. The wiring substrate can include an electrical interface to a test controller and a plurality of electrical wiring composing electrical paths between the electrical interface and ones of the probes, and the wiring substrate can comprise a first portion on which the electrical interface is disposed and a second portion composing the probe head assembly. The second portion of the wiring substrate can be moveable with respect to the first portion of the wiring substrate.
Type:
Application
Filed:
October 20, 2006
Publication date:
June 7, 2007
Applicant:
FORMFACTOR, INC.
Inventors:
Eric Hobbs, Alexander Slocum, Benjamin Eldridge, Keith Breinlinger, Shawn Powell
Abstract: Probes of a probe card assembly can be adjusted with respect to an element of the probe card assembly, which can be an element of the probe card assembly that facilitates mounting of the probe card assembly to a test apparatus. The probe card assembly can then be mounted in a test apparatus, and an orientation of the probe card assembly can be adjusted with respect to the test apparatus, such as a structural part of the test apparatus or a structural element attached to the test apparatus.
Type:
Application
Filed:
December 2, 2005
Publication date:
June 7, 2007
Applicant:
FormFactor, Inc.
Inventors:
Benjamin Eldridge, Eric Hobbs, Gaetan Mathieu, Makarand Shinde, Alexander Slocum
Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads.
Abstract: Contact structures exhibiting resilience or compliance are formed. The contact structures may be formed on a sacrificial substrate. The contact structures are attached to an array of electrical connections on a substrate to form a contact assembly. The electrical connections on the substrate may be metallic pads.
Type:
Grant
Filed:
December 28, 2001
Date of Patent:
June 5, 2007
Assignee:
FormFactor, Inc.
Inventors:
Benjamin Niles Eldridge, Gary William Grube, Igor Yan Khandros, Gaetan L. Mathieu
Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.
Type:
Grant
Filed:
February 18, 2004
Date of Patent:
May 15, 2007
Assignee:
FormFactor, Inc.
Inventors:
Timothy E. Cooper, Benjamin N. Eldridge, Igor Y. Khandros, Rod Martens, Gaetan L. Mathieu
Abstract: One or more testers wirelessly communicate with one or more test stations. The wireless communication may include transmission of test commands and/or test vectors to a test station, resulting in testing of one or more electronic devices at the test station. The wireless communication may also include transmission of test results to a tester. Messages may also be wirelessly exchanged.
Type:
Grant
Filed:
October 21, 2003
Date of Patent:
May 15, 2007
Assignee:
FormFactor, Inc.
Inventors:
Igor Y. Khandros, Benjamin N. Eldridge, A. Nicholas Sporck, Charles A. Miller
Abstract: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.
Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.
Type:
Grant
Filed:
June 7, 1999
Date of Patent:
May 8, 2007
Assignee:
Formfactor, Inc.
Inventors:
Mohammad Eslamy, David V. Pedersen, Harry D. Cobb
Abstract: Apparatuses and methods for cleaning test probes used in a semiconductor testing machine of the type having a plurality of test probes configured to contact the surface of a semiconductor wafer to test one or more dies formed thereon. In one embodiment, the apparatus includes a roller-support arm and a cylindrical roller supported by the roller-support arm. The roller has an outer surface comprising a sticky material. Debris on the probes will adhere to the sticky material as roller is rolled across tips of the probes. The probes are thereby cleaned.
Abstract: An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.
Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.
Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.
Type:
Grant
Filed:
December 30, 2003
Date of Patent:
April 10, 2007
Assignee:
FormFactor, Inc.
Inventors:
David V. Pedersen, Benjamin N. Eldridge, Igor Y. Khandros
Abstract: An electronic device is moved into a first position with respect to probes for making electrical contact with the device. The electronic device is then moved into a second position in which the electronic device is pressed against the probes, compressing the probes. The movement into the second position includes two components. One component of the movement tends to press the electronic device against the probes, compressing the probes and inducing a stress in the probes. The second movement tends to reduce that stress. Test data are then communicated to and from the electronic device through the probes.
Type:
Grant
Filed:
December 20, 2002
Date of Patent:
April 10, 2007
Assignee:
FormFactor, Inc.
Inventors:
Timothy E. Cooper, Benjamin N. Eldridge, Igor Y. Khandros, Rod Martens, Gaetan L. Mathieu
Abstract: A base controller disposed in a test cassette receives test data for testing a plurality of electronic devices. The base controller wirelessly transmits the test data to a plurality of wireless test control chips, which write the test data to each of the electronic devices. The wireless test control chips then read response data generated by the electronic devices, and the wireless test control chips wirelessly transmit the response data to the base controller.
Type:
Grant
Filed:
April 8, 2004
Date of Patent:
April 10, 2007
Assignee:
FormFactor, Inc.
Inventors:
Igor Y. Khandros, Benjamin N. Eldridge, Charles A. Miller, A. Nicholas Sporck
Abstract: An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals.
Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
Type:
Grant
Filed:
March 4, 2005
Date of Patent:
March 27, 2007
Assignee:
FormFactor, Inc.
Inventors:
Gary W. Grube, Igor Y. Khandros, Benjamin N. Eldridge, Gaetan L. Mathieu, Poya Lotfizadeh, Jim Chih-Chiang Tseng
Abstract: Improved lithographic type microelectronic spring structures and methods are disclosed, for providing improved tip height over a substrate, an improved elastic range, increased strength and reliability, and increased spring rates. The improved structures are suitable for being formed from a single integrated layer (or series of layers) deposited over a molded sacrificial substrate, thus avoiding multiple stepped lithographic layers and reducing manufacturing costs. In particular, lithographic structures that are contoured in the z-direction are disclosed, for achieving the foregoing improvements. For example, structures having a U-shaped cross-section, a V-shaped cross-section, and/or one or more ribs running along a length of the spring are disclosed. The present invention additionally provides a lithographic type spring contact that is corrugated to increase its effective length and elastic range and to reduce its footprint over a substrate, and springs which are contoured in plan view.
Abstract: A method and system for sealing or covering exposed fuses on a semiconductor device are disclosed. A semiconductor device prober incorporating a spray device for applying a sealing compound to individual fuses on a semiconductor device subsequent to testing the semiconductor device is disclosed. A method and system for sealing exposed fuses on a semiconductor device is disclosed which allows the sealing step to be performed either prior to or following singulation of the semiconductor device into individual dice.