Abstract: A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.
Type:
Grant
Filed:
December 11, 2003
Date of Patent:
October 10, 2006
Assignee:
Fortelink, Inc.
Inventors:
Sweyyan Shei, Ming Yang Wang, Vincent Chiu, Neu Choo Ngui
Abstract: Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it.
Type:
Grant
Filed:
December 11, 2003
Date of Patent:
October 3, 2006
Assignee:
Fortelink, Inc.
Inventors:
Ming Yang Wang, Sweyyan Shei, Vincent Chiu
Abstract: An apparatus for emulating the behavior of an electronic device under test (DUT) includes a computer and one or more resource boards containing emulation resources suitable for emulating portions of the DUT. Each resource board includes transaction device for communicating with one another and with the computer network via data packets transmitted over a packet routing network. The packet routing network and the transaction device on each resource board provide “virtual signal paths” between input and output terminals of resources mounted on separate resource boards. To do so, a transaction device on one resource board sends packets containing data indicating output signal states of local emulation resources to a transaction device on another resource board when then drives signals supplied to input terminals of its local emulation resources to the states indicated by the data conveyed in the packet.
Type:
Grant
Filed:
June 16, 2003
Date of Patent:
July 4, 2006
Assignee:
Fortelink, Inc.
Inventors:
Ming Yang Wang, Sweyyan Shei, Vincent Chiu