Abstract: A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.

Abstract: A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor.

Abstract: A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.

Abstract: A polarity switch circuit for a charger is disclosed. The circuit includes a polarity switch unit and an input control unit. The polarity switch unit includes an input end, an output end, a correct-direction connecting circuit, and a reverse-direction connecting circuit. The correct-direction connecting circuit has a first switch unit and a second switch unit. When the load is plugged correctly, the positive input node is connected to the positive output node by the first switch unit, and the negative input node is connected to the negative output node by the second switch unit. The reverse-direction connecting circuit includes a third switch unit and a fourth switch unit. When the load is plugged reversely, the positive input node is connected to the negative output node by the third switch unit, and the negative input node is connected to the positive output node by the fourth switch unit.

Abstract: A test mode controller comprises an enable signal generator, a control signal generator, and a latch. The enable signal generator receives a power signal and a second control signal, and generates a first enable signal and a second enable signal respectively to the latch and the control signal generator. The control signal generator receives a power indicating voltage and a reference voltage, and generates the first control signal to the latch when the first enable signal is enabled. The latch receives the first control signal, and generates the second control signal according to the first control signal when the second enable signal is enabled. The second control signal controls a chip to operate in a test mode or a normal mode. Accordingly, the test mode controller may reduce the test time without a test pin, and may also reduce the chip area and the package cost.

Abstract: A circuit apparatus includes an input end, an output end, an enable module, a first function module and a second function module. The enable module couples to the input end for receiving an input voltage and outputs an enable signal while the input voltage falls within a first voltage scope. The first function module couples to the enable module and the output end, and performs a test mode according to the enable signal so as to output a test result to the output end. The second function module couples to the input end for receiving the input voltage via the input end and performs a standard mode while the input voltage falls within a second voltage scope.

Abstract: A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.

Abstract: A layout of a power MOSFET includes a first zigzag gate structure located on a substrate of the power MOSFET and having a first side and a second side, a first contact located on the substrate and at the first side of the first zigzag gate structure, and a second contact structure located on the substrate and at the second side of the first zigzag gate structure.

Abstract: A seal-ring structure includes a substrate, a source/drain layer, a first dielectric layer, a first lower metal layer, a gate layer and a second lower metal layer. The source/drain layer is disposed within the substrate. The first dielectric layer is disposed over the substrate. The first lower metal layer is disposed over the first dielectric layer and coupled to the source/drain layer via a first contact. The gate layer is disposed within the first dielectric layer. The second lower metal layer is disposed over the first dielectric layer and coupled to the gate layer via a second contact.

Abstract: A semiconductor chip includes an integrated circuit region, at least one alignment indicator region and a seal-ring. The alignment indicator region is disposed near the integrated circuit region. The seal-ring surrounding the integrated circuit region is disposed outside of the integrated circuit region, and is formed as a mark for alignment on the alignment indicator region at a corner of the semiconductor chip. A manufacturing process of the seal-ring structure is also disclosed.

Abstract: A method for programming a one-time programmable memory of an integrated circuit includes the following steps: writing an instruction set into the one-time programmable memory via a first programmable interface, running a programmable self-instruction of the instruction set, and writing a proofreading value of the integrated circuit into the one-time programmable memory via a second programmable interface. The present method takes full advantage of the one-time programmable memory. Manufacturers for manufacturing integrated circuits don't write various proofreading values corresponding to different applications. A producing efficiency can be increased, and a producing cost can be decreased. The present integrated circuit needs not to be communicated with an addition storing device, so the present integrated circuit has a simple construction, and the cost can be decreased. Since the present integrated circuit can write perform a proofreading self-instruction, the producing cost can be decreased.

Abstract: An integrated circuit (IC) includes a micro control unit (MCU), a one-time programmable (OTP) memory directly connected with the MCU, an electrical charge pump having an output port and an enable port connected to the MCU, and a switching circuit having a control port connected to the MCU, a first input port connected to the output port of the electrical charge pump, a second input port connected to a power source of the MCU, and an output port connected to the OTP memory to provide an operating voltage and a recording voltage for the OTP memory. Because the OTP memory can choose the operating voltage or the recording voltage, a measuring apparatus using this IC doesn't need an external power source to provide a VDD voltage being 5.8 volts. Therefore, a power consuming of the IC can be reduced.