Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Grant
Filed:
December 17, 2007
Date of Patent:
May 4, 2010
Assignee:
Institute of Computer Science, Foundation for Research and Technology -Hellas
Abstract: A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.
Type:
Grant
Filed:
July 31, 2007
Date of Patent:
October 13, 2009
Assignee:
Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas, Foundation for Research and Technology Hellas (Forth)
Inventors:
Christos P. Sotiriou, Pavlos Mattheakis
Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.
Type:
Application
Filed:
October 25, 2007
Publication date:
July 16, 2009
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")
Inventors:
Christos P. Sotiriou, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Grant
Filed:
December 23, 2005
Date of Patent:
January 8, 2008
Assignee:
Institute of Computer Science, Foundation for Research and Technology - Hellas (“ICS”)
Abstract: According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.
Type:
Application
Filed:
January 12, 2006
Publication date:
September 28, 2006
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")
Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Application
Filed:
December 23, 2005
Publication date:
July 13, 2006
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")
Abstract: The present invention provides a method and an apparatus for the in vivo, non-invasive, early detection of alterations and mapping of the grade of these alterations, caused in the biochemical and/or in the functional characteristics of epithelial tissues during the development of tissue atypias, dysplasias, neoplasias and cancers. The method is based, at least in part, on the simultaneous measurement of the spatial, temporal and spectral alterations in the characteristics of the light that is re-emitted from the tissue under examination, as a result of a combined tissue excitation with light and special chemical agents. The topical or systematic administration of these agents result in an evanescent contrast enhancement between normal and abnormal areas of tissue. The apparatus enables the capturing of temporally successive imaging in one or more spectral bands simultaneously.
Type:
Application
Filed:
November 3, 2005
Publication date:
June 29, 2006
Applicant:
THE FOUNDATION OF RESEARCH AND TECHNOLOGY HELLAS
Abstract: The present invention relates to nucleic acids comprising a nucleotide sequence encoding at least a portion of an enzyme which catalyzes the synthesis of chitin in arthropods, inhibitors directed to said enzyme, and a method for developing said inhibitors.
Type:
Application
Filed:
June 26, 2002
Publication date:
September 4, 2003
Applicant:
Foundation for Research and Technology - Hellas Institute of Molecular Biology and Biotechnology
Abstract: The present invention provides a method and an apparatus for the in vivo, non-invasive, early detection of alterations and mapping of the grade of these alterations, caused in the biochemical and/or in the functional characteristics of epithelial tissues during the development of tissue atypias, dysplasias, neoplasias and cancers. The method is based, at least in part, on the simultaneous measurement of the spatial, temporal and spectral alterations in the characteristics of the light that is re-emitted from the tissue under examination, as a result of a combined tissue excitation with light and special chemical agents. The topical or systematic administration of these agents result in an evanescent contrast enhancement between normal and abnormal areas of tissue. The apparatus enables the capturing of temporally successive imaging in one or more spectral bands simultaneously.
Type:
Application
Filed:
January 16, 2003
Publication date:
August 28, 2003
Applicant:
Foundation for Research and Technology - Hellas (FORTH)
Abstract: A method of producing an ohmic contact to p-type silicon carbide comprising two layers, the first one comprising nickel silicide and the second one comprising titanium carbide is disclosed. The deposited layers are annealed to convert at least a part of deposited metals to nickel silicide and titanium carbide. The contact is formed by reaction between the metals and the semiconductor, and thus the in-situ simultaneous formation of metal silicide and carbide suppress the release of excess carbon at the contact interface. Noble metals may be deposited preferably in between titanium and nickel to improve the contact morphology.
Type:
Grant
Filed:
October 4, 2001
Date of Patent:
July 29, 2003
Assignee:
Foundation for Research & Technology-Hellas
Inventors:
Konstantinos Zekentes, Konstantin V. Vassilievski
Abstract: The present invention relates to nucleic acids comprising a nucleotide sequence encoding at least a portion of an enzyme which catalyzes the synthesis of chitin in arthropods, inhibitors directed to said enzyme, and a method for developing said inhibitors.
Type:
Grant
Filed:
January 19, 1999
Date of Patent:
October 15, 2002
Assignee:
Foundation for Research and Technology-Hellas
Abstract: The invention relates to a pipeline buffer for simultaneously transferring N words at each of a succession of clock cycles (CK), comprising N one-word side memories (M0-M3) successively connected such that successive memories each are accessed with one clock cycle delay. The N memories are subjected to the same read or write cycles by control circuitry.
Type:
Grant
Filed:
July 24, 1995
Date of Patent:
June 30, 1998
Assignee:
Foundation of Research and Technology-Hellas