Patents Assigned to Foundry Networks, LLC
  • Patent number: 7832009
    Abstract: Techniques for detecting and responding to attacks on computer and network systems including denial-of-service (DoS) attacks. A packet is classified as potentially being an attack packet if it matches an access control list (ACL) specifying one or more conditions. One or more actions may be performed responsive to packets identified as potential attack packets. These actions may include dropping packets identified as potential attack packets for a period of time, rate limiting a port over which the potential attack packets are received for a period of time, and other actions.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: November 9, 2010
    Assignee: Foundry Networks, LLC
    Inventors: Sheng-Yih Wang, Ron Talmor
  • Patent number: 7822049
    Abstract: A system and method which enables a provider network to run a loop detection protocol in a customer network communicably coupled to it. The provider network runs a loop detection protocol and the customer network either runs a different protocol or none. The provider network determines its root bridge, or designated customer bridge, which is used to control loop detection decisions for the customer network. A BPDU or other protocol packet received from the customer network is tunneled through the provider network to the designated customer bridge. The designated customer network then processes the received BPDU in accordance with a loop detection instance for the customer network. The designated customer bridge then produces control messages in response to the processing and forwards those messages to the customer network. The control messages may include port state controls for ports in the customer network.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: October 26, 2010
    Assignee: Foundry Networks, LLC
    Inventors: Jordi Moncada-Elias, Rajiv Ramanathan
  • Patent number: 7817659
    Abstract: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: October 19, 2010
    Assignee: Foundry Networks, LLC
    Inventors: Yuen Fai Wong, Yu-Mei Lin, Richard A. Grenier