Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.
Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.
Abstract: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile memory (118). The memory management module (116) is also adapted to refresh the volatile memory (118) at a refresh rate which causes refresh-based errors and to correct the refresh-based errors. Also disclosed is a method for reduced power consumption by a volatile memory requiring refreshing to avoid data loss in which such a volatile memory is refreshed (122) at a refresh rate. All defective bits are detected (124) at the refresh rate. An error correction code is selected (126) for correcting the defective bits.
Abstract: In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.
Type:
Grant
Filed:
April 23, 2008
Date of Patent:
March 6, 2012
Assignee:
Frankfurt GmbH, LLC
Inventors:
Marc Stimak, Terry C. Brown, Mike Minnick