Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.
Type:
Grant
Filed:
May 23, 2016
Date of Patent:
January 9, 2018
Assignees:
GLOBALFOUNDRIES Inc., Fraunhofer Gesellschaft zur Foerderung der angewandted Forschung e.V., NaMLab gGmbH
Inventors:
Johannes Mueller, Stefan Mueller, Stefan Flachowsky