Abstract: A crosspoint switch architecture implements high-speed packet switches and incorporates a power-saving bias control circuit with each switch cell. Each switch cell is equipped with two memory cells and a bias control circuit. Power savings are obtained by controlling the bias current of the switch cell as a function of the switch state. Although the additional circuitry accompanying each switch cell adds complexity and a minimal additional power consumption, the power saving realized in the switch cell results in a crosspoint switch with much lower power consumption as compared to existing architectures. The presence of two bits of memory for each switch core allows for fast reconfiguration. The result is an overall power savings and lower cost design.