Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.

Abstract: A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request.

Abstract: A method and apparatus are provided for detecting a rotor lock condition in a sensorless permanent magnet synchronous motor. A BEMF observer determines an estimated rotor speed {circumflex over (?)} and a first BEMF voltage value in an estimated rotor-related ?,? reference frame. In addition, a second estimated BEMF voltage value is calculated in a rotor-related d,q reference frame based on at least a first motor constant and an estimated rotor speed {circumflex over (?)}. After generating a BEMF error filter value from the first and second estimated BEMF voltage values and calculating a BEMF error threshold value as a function of the estimated rotor speed {circumflex over (?)} that is subject to a minimum threshold BEMF value, a rotor lock condition is detected based on at least the BEMF error filter value and the BEMF error threshold value.

Abstract: A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. A first access transistor includes a first current electrode coupled to a bit line; a second current electrode coupled to the first node, and a control electrode coupled to a word line. A match line transistor includes a first current electrode coupled to a match line; a second current electrode coupled to a second supply voltage and a control electrode coupled to the first node.

Abstract: Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset.

Abstract: A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. The controller records an alteration log authentication code in secure memory. The alteration log is indirectly related to a most recent image stored in the tracked memory. Authentication of the image of the alteration log is used as a proxy for authentication of the image stored in tracked memory, which is performed only when the tracked memory is modified. Use of the contents of the alteration log as a proxy for the contents of tracked memory accelerates the startup time of the system.

Abstract: A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

Abstract: A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.

Abstract: IC device comprising a plurality of functional components arranged into self-test cells. The IC device is configurable into a first self-test configuration comprising a first set of self-test partitions. Each self-test partition within the first set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the first set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the first self-test configuration. The IC device is configurable into a second self-test configuration comprising a second set of self-test partitions. Each self-test partition within the second set comprising at least one self-test cell. Functional components of the self-test cell(s) of each self-test partition within the second set are arranged to be configured into at least one scan-chain for said self-test partition when the IC device is configured into the second self-test configuration.

Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Abstract: A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.

Abstract: A processor uses a dedicated buffer to reduce the amount of time needed to execute memory copy operations. For each load instruction associated with the memory copy operation, the processor copies the load data from memory to the dedicated buffer. For each store operation associated with the memory copy operation, the processor retrieves the store data from the dedicated buffer and transfers it to memory. The dedicated buffer is separate from a register file and caches of the processor, so that each load operation associated with a memory copy operation does not have to wait for data to be loaded from memory to the register file. Similarly, each store operation associated with a memory copy operation does not have to wait for data to be transferred from the register file to memory.

Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

Abstract: A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Abstract: A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.

Abstract: An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an ON-state, waiting an amount of waiting an amount of time tB after the current within the switched current circuit increases above a current threshold, and switching the switched current circuit into an OFF-state after waiting the time tB. Further, a duration of time tA1 between switching the switched current circuit in the OFF-state and the point at which the current within the switched current circuit decreases below the current threshold is determined, and the method includes waiting a time tA2 after the current within the switched current circuit decreased below the current threshold, the time tA2 based at least in part on the time tA1, after which the switched current circuit is switched into the ON-state.

Abstract: A dual-band Doherty amplifier and method therefor are provided. The dual-band Doherty amplifier includes a first amplifier gain element, a first transmission line coupled to a first output of the first amplifier gain element, a second amplifier gain element, a second transmission line coupled to a second output of the second amplifier gain element, and a controller configured, when a signal to be amplified is in a first band, to provide a first bias signal to a first bias input of the first amplifier gain element and a second bias signal to a second bias input of the second amplifier gain element and, when the signal is in a second band, to provide the second bias signal to the first bias input of the first amplifier gain element and the first bias signal to the second bias input of the second amplifier gain element.