Abstract: A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

Abstract: A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter.

Abstract: A Code Division Multiple Access (CDMA) post-correlation processing system (12) for delay locked loop processing reduces the control data rate into a delay locked loop (DLL) processor and the number of required interpolation operations by executing a portion of the interpolation operations at a symbol data rate rather than at a chiprate. Specifically, an interpolator (16) generates time shifted chip samples based on input CDMA chip samples. First and second correlators (22, 24) extract ontime control and data symbol samples, respectively, from ontime input CDMA chip samples. A third correlator (26) extracts first non-ontime control symbol samples from non-ontime CDMA chip samples. The first non-ontime control symbol samples are then input with the ontime control symbol samples to a post-correlation interpolator (28) operating at a symbol rate to generate second non-ontime symbol samples necessary for Delay Locked Loop (DLL) processing.