Abstract: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
Type:
Grant
Filed:
December 31, 2007
Date of Patent:
May 10, 2011
Assignee:
Freescale Semicondoctor, Inc.
Inventors:
David C. Holloway, Michael D. Snyder, Suresh Venkumahanti