Abstract: A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

Abstract: A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.

Abstract: A digital decoder, used in a reconfigurable circuit, for decoding digital pulses includes a phase indicator module having inputs coupled to a reference pulse input and a data pulse input. The phase indicator module has timing information outputs that provide logic values indicative of rising and falling edges of pulses occurring on the reference pulse input and the data pulse input. A phase decoder module has inputs coupled to the timing information outputs, and outputs decoded binary data values. In operation, the phase decoder module compares at least two of the logic values at the timing information outputs with a signal representative leading and trailing edges of a pulse applied to one of the phase inputs to determine a pulse arrival order sequence on the phase inputs and thereby provide the decoded binary data values.

Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.

Abstract: Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.