Abstract: A device 20 includes a substrate 22 having an integrated circuit (IC) die 24 coupled thereto. A bond wire 28 interconnects a die bond pad 32 on the IC die 24 with an insulated bond pad 36. Another bond wire 38 interconnects a die bond pad 42 on the IC die 24 with another insulated bond pad 46. The bond wires 28 and 38 serve as radiating elements of a dipole antenna structure 64. A reflector 72 and director 74 can be located on the substrate 22 and/or the IC die 24 to reflect and/or direct a radiation pattern 66 emitted by or received by the antenna structure 64. A trace 82 can be interconnected between the insulated bond pads 36, 46 to form a folded dipole antenna structure 84.

Abstract: A lead frame for a semiconductor device includes at least one row of contact terminals and a die pad for receiving an integrated circuit die. An isolation material is located between the contact terminals and the die pad. The isolation material electrically isolates adjacent lead fingers from each other and from the die pad. The isolation material also holds the lead fingers in place during a wire bonding operation and thus the bottom of the lead frame does not have to be taped during the assembly process, which saves taping and detaping steps from being performed. The isolation material also prevents resin bleed problems that sometimes occur when using tape. If a sawing step is performed, the saw need only cut through the isolation material instead of a metal, and thus saw blade life is improved.

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

Abstract: A method (700) and apparatus (600) are described for performing decision voting in connection with a parallel ACS unit (110) and track buffer (112) in an Ultrawide Bandwidth (UWB) receiver having a parallel DECODER for decoding a message sequence encoded according to a convolutional code. Outputs from the track buffer can be input to a voting unit (620) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: A small transceiver device and antenna system has an insulating layer with first and second surfaces. A transmit loop element having transmit loop segments is formed on the first surface. The transmit loop segments are disposed in a transmit zigzag configuration. A receive loop element having receive loop segments is formed on the second surface. The receive loop segments are disposed in a receive zigzag configuration. Each receive loop segment in the receive zigzag configuration is skewed with respect to a closest transmit loop segment disposed in the transmit zigzag configuration. The transmit loop segments can be grouped in two or more transmit zigzag configurations, and the receive loop segments can be grouped in two or more receive zigzag configurations.

Abstract: A system and method for obtaining processor diagnostic data. The method can include receiving a instruction, enabling write access of an output stream to a diagnostic memory, writing to the diagnostic memory at a first frequency, and reading from the diagnostic memory at a second frequency where the first frequency is greater than the second frequency.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a VBE and a multiplied ?VBE, so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ?VBE loop. The ?VBE loop can be the portion of the circuit involved in generating the ?VBE voltage. Other embodiments are disclosed in this application.

Abstract: A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value.

Abstract: A method for cleaning, especially by removing etch residue (e.g., polymers or particles) from a semiconductor structure, and a cleaning chemistry is described. The method of cleaning includes placing the semiconductor structure with an etch residue particle on it in a chemistry to remove the particle, wherein the active component of the chemistry consists of a carboxylic acid having equal numbers of COOH and OH groups. In one embodiment, the carboxylic acid is tartaric acid. In one embodiment, the chemistry further comprises water.

Abstract: A leadframe (40) for a semiconductor device has a radially extending leads (42) having inner lead portions (44) and outer lead portions (46), and a dam bar (48) that mechanically connects the leads (42) together near the outer lead portions (46). The inner lead portions (44) define an open area having a central region and the dam bar (48) defines a leadframe outer perimeter. A generally X-shaped die support member has arms (50) that extend from the leadframe outer perimeter and meet at the central region. A heat sink includes sections (64) that are formed between adjacent pairs of the die support member arms (50). The heat sink sections (64) are connected to the die support member arms (50) with down set tie bars (66) such that the heat sink lays in a plane below a plane of the die support member arms (50).

Abstract: A lead frame (10) for a quad flat non-leaded semiconductor package (606), includes a tie bar (12), a first group of leads (22) extending a first length from the tie bar (12) in a transverse direction (Y), and a second group of leads (24) extending a second length from the tie bar (12) in the transverse direction (Y). The second length is greater than the first length, and leads from the first and second group of leads (22, 24) alternate in a longitudinal direction (X) along the tie bar (12) so that the first and second groups of leads are staggered. The second group of leads (24) is displaced from the first group of leads (22) in a Z-direction (Z) perpendicular to both the transverse (Y) and longitudinal (X) directions. The leads of the first and second groups of leads (22, 24) each have a respective contact terminal (26 and 28) at their distal ends. The contact terminals (26 and 28) each have a contact face (40 and 42) in a contact plane (44).

Abstract: A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.

Abstract: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).

Abstract: Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value.

Abstract: A method for searching within a data block for a data chunk having a predefined value, the method includes: fetching, by a processor, a data block search instruction; fetching, a data unit that includes multiple data chunks; wherein at least one data chunk within the data unit belongs to the data block; deciding whether to use a mask for data chunk level masking; searching, by a hardware accelerator, for a valid data chunk within the fetched data unit that has the predefined value; wherein the searching comprising applying a mask; wherein a valid data chunk in an non-masked data chunk that belongs to the data block; and determining whether to update the value of the mask and whether to fetch a new data unit that belongs to the data block.