Abstract: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.

Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Abstract: A system for imaging a structure of an object is provided. The imaging system includes a degree-of-focus determination module that may comprise logic for taking into account at least one of a first and a second dimension of a topological element of the structure to be imaged. An image processing module of the system may comprise: a control module for controlling a motorized focus driver; a memory for storing images; and said degree-of-focus determination module. The imaging system may comprise: a stage; a motorized focus driver for driving the stage; at least one of microscope optics, a lens, an illumination system; a camera; and an image processing module.

Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.

Abstract: Method and apparatus are provided for linearized balanced signal mixing. A signal mixing circuit (10) for translating a radio frequency (RF) signal is provided comprising an input amplifier (12), a mixer network (14), and an output buffer amplifier (18). The input amplifier (12) is configured to produce an amplified RF signal and cancel an input third-order intermodulation (IM3) distortion in the amplified RF signal with a cross-coupled feedback amplifier (13). The mixer network (14) is configured to produce an intermediate frequency (IF) signal based on the amplified RF signal and a local oscillator signal. The output amplifier (18) is configured to buffer the IF signal and cancel an output IM3 distortion in the IF signal with a cross-coupled feedback amplifier (19). The input amplifier (12) and cross-coupled feedback amplifier (13) also serve as a bias current source for the mixer network (14), thus lowering the supply voltage required for the mixing circuit (10).

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.