Abstract: A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.

Abstract: A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Abstract: An integrated circuit (IC) includes a reference voltage generator, a voltage regulator, a reset controller, and a voltage monitoring circuit. The reference voltage generator generates first and second reference voltages, and the voltage regulator generates a supply voltage. The reset controller stabilizes the first and second reference voltages in a first predetermined time period, and generates a power down signal after the first predetermined time period. The voltage monitoring circuit compares a level of the supply voltage with a level of the second reference voltage after the first predetermined time period and generates a (low) voltage monitor signal. The reset controller also generates a (high) reset signal when the supply voltage is greater than the second reference voltage.

Abstract: An electronic design automation (EDA) tool for increasing the fault coverage of an integrated circuit (IC) design includes a processor that inserts at least one XOR gate, an AND gate, an OR gate and a multiplexer between observation test points and an existing first scan flip-flop of the IC design. The XOR gate provides an observation test signal to the first scan flip-flop by way of the AND gate, the OR gate, and the multiplexer such that the observation test signal covers the presence of faults at the observation test points. The first scan flip-flop outputs a data input signal, a set of test patterns, and a first set of test signals based on the observation test signal to indicate whether the IC design is faulty or not. A testable IC that can be structurally tested is fabricated using the IC design.