Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: A time-varying pitch of a signal may be estimated by processing a sequence of frames of the speech signal. An estimated fractional chirp rate may be computed for each frame of the sequence of frames, and the estimated fractional chirp rates may be used to compute a pitch template for the sequence, where the pitch template indicates the time-varying pitch of the signal subject to a scale factor. A first pitch estimate for each frame of the sequence of frames may be computed by computing a scale factor and multiplying the pitch template by the scale factor. A second pitch estimate may be computed from the first pitch estimate by identifying peaks in the frequency representations using the first pitch estimates and fitting a parametric function to the peaks.

Abstract: Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses.

Abstract: A time-varying pitch of a signal may be estimated by processing a sequence of frames of the speech signal. An estimated fractional chirp rate may be computed for each frame of the sequence of frames, and the estimated fractional chirp rates may be used to compute a pitch template for the sequence, where the pitch template indicates the time-varying pitch of the signal subject to a scale factor. A first pitch estimate for each frame of the sequence of frames may be computed by computing a scale factor and multiplying the pitch template by the scale factor. A second pitch estimate may be computed from the first pitch estimate by identifying peaks in the frequency representations using the first pitch estimates and fitting a parametric function to the peaks.

Abstract: An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding frameless packets. One of the methods includes receiving a data payload to be transmitted. The data payload is partitioned into multiple payload words, each payload word being of a predetermined size. A first sync word is added to each of the multiple payload words. A control word comprising label and an error checking value is added. A second sync word is added to the label and error checking word. If one or more counter criteria are satisfied while transmitting the multiple payload words, an idle word is transmitted before transmitting the label and error checking word.

Abstract: Systems and techniques for network on a chip based computer architectures and distributing data without shared pointers therein are described. A described system includes computing resources; and a memory resource configured to maintain a dedicated memory region of the memory resource for distributed read operations requested by the computing resources. The computing resources can generate a packet to fetch data from the dedicated memory region without using memory addresses of respective data elements. The memory resource can receive the first packet, determine whether the first packet indicates the distributed read operation, and determine that the dedicated memory region is non-empty. Further, the memory resource can fetch one or more data elements from the dedicated memory region based on the first packet indicating the distributed read operation and the dedicated memory region being non-empty, and send a packet that includes the one or more fetched data elements.

Abstract: A router that requests a reservation for an egress port prior to dequeuing a received packet. A reservation is granted only if there is space on the egress port for at least a maximum size packet. An ingress processor requests allocation of a packet buffer. An allocator grants the packet buffer, but if there are fewer than a threshold number of buffers available, the ingress processor will not accept the grant unless the received packet is to be routed to a port inside the device comprising the router. This conserves the packet buffer(s) for packets destined for locations within the device. After a reservation is obtained and a packet buffer has been accepted, the ingress processor begins dequeuing a received packet from an ingress port queue to the buffer, and provides an identifier of the buffer to an egress processor. The identifier is enqueued by the egress processor. After the identifier is dequeued, the egress processor copies the packet from the buffer to an egress queue and releases the buffer.

Abstract: In one aspect, a method includes receiving an identifier; obtaining a plurality of prompts using the identifier, wherein a first prompt corresponds to a first character of an access code, and a second prompt corresponds to a second character of the access code; causing the first prompt and the second prompt to be presented on a display at locations corresponding to a first alternative; causing third prompts and fourth prompts to be presented on the display at locations corresponding to a second alternative; receiving an audio signal comprising speech spoken by a user; and determining whether the audio signal comprises the user speaking the first prompt followed by the second prompt.

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: A time-varying pitch of a signal may be estimated by processing a sequence of frames of the speech signal. An estimated fractional chirp rate may be computed for each frame of the sequence of frames, and the estimated fractional chirp rates may be used to compute a pitch template for the sequence, where the pitch template indicates the time-varying pitch of the signal subject to a scale factor. A first pitch estimate for each frame of the sequence of frames may be computed by computing a scale factor and multiplying the pitch template by the scale factor. A second pitch estimate may be computed from the first pitch estimate by identifying peaks in the frequency representations using the first pitch estimates and fitting a parametric function to the peaks.

Abstract: An input signal may be classified by computing correlations between feature vectors of the input signal and feature vectors of reference signals, wherein the reference signals correspond to a class. The feature vectors of the input signal and/or the reference signals may be segmented to identify portions of the signals before performing the correlations. Multiple correlations of the segments may be combined to produce a segment score corresponding to a segment. The signal may then be classified using multiple segment scores, for example by comparing a combination of the segment scores to a threshold.

Abstract: A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.

Abstract: Devices, systems and methods are provided for writing, by a plurality of computing resources, to contiguous memory addresses of memory that supports random access, without having to specify actual write addresses of the memory.

Abstract: Systems, devices, and techniques for processor synchronization are described. A described system includes sending, from first processors, release requests to an inclusion monitor, the release requests including an identifier tag; sending, from a second processor, an acquire request to the inclusion monitor circuitry, the acquire request including a weight value and the identifier tag; creating a content addressable memory (CAM) entry based on a receipt of at least one of the release or acquire requests; maintaining a count of the release requests that correspond to the identifier tag by using the entry's arrival counter; causing the first processors to stall if the entry's arrival counter does not satisfy a threshold criterion specified by the entry's weight value or if the acquire request has not been received; storing the acquire request's weight value as the entry's weight value; and releasing the first processors if the entry's arrival counter satisfies the criterion.

Abstract: Systems, devices, and techniques for processor synchronization are described. A described system includes exclusion monitor circuitry, a content addressable memory (CAM) coupled with the exclusion monitor circuitry, and processors coupled with the exclusion monitor circuitry. The processors can perform synchronization via the exclusion monitor circuitry using an identifier tag. The exclusion monitor circuitry can utilize the CAM to store information for handling one or more named mutual exclusions. The exclusion monitor circuitry and the CAM can be configured to concurrently handle multiple identifier tags that correspond to different mutual exclusions.