Abstract: High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves as an inverting amplifier of a global sense amp for reading the segment sense amp. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating low data and high data by the sense amps for realizing fast access with dynamic operation. Furthermore, a buffered data path is used for achieving fast access and amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described.

Abstract: Low power carbon nanotube memory is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, a first tri-state inverter serves as an inverting amplifier of a global sense amp, and a second tri-state inverter serves as a bypass circuit for bypassing output from previous memory block. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating high data and low data by the sense amps for realizing low power with dynamic operation. In particular, amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. And buffered data path is used for achieving fast data transfer. Additionally, alternative circuits and memory cell structures are described.

Abstract: DRAM includes a tunable gain amp serving as a local sense amp, wherein the tunable gain amp is connected to a local bit line for reading a memory cell including a pass transistor and a capacitor, and gain of the tunable gain amp is adjusted by setting a local amp voltage for reading the memory cell more effectively with optimized gain. And a global sense amp is connected to the local sense amp for receiving a read output. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as a reference signal. In addition, alternative circuits are described.