Abstract: A clock and data recovery circuit has a voltage controlled oscillator that provides a clocking signal synchronized to a received serialized data. A multiple phase generator converts the clocking signal to a plurality of multiple phased clocking signals. A data capture device acquires the serialized data with each of the plurality of multiple phased clocking signals to create multiple phased data signals. A phase detector determines if the clocking signal is in phase with the recovered serialized data and providing a lead signal and a lag signal indicating whether the clocking signal is in phase with the recovered serialized data. A frequency initializing device assists acquisition of lock of the voltage controlled oscillator to a reference clock signal. A recovered data selector selects which of the multiple phased data signals are to be transferred to external circuitry for further processing.

Abstract: A spread spectrum clock generator comprises a conventional closed-loop VCO and an open-loop VCO where both are coupled to the same point of the PLL. Both VCOs comprise a V-to-I converter followed by a current-controlled oscillator and are identical in design but only the open-loop VCO receives the modulation current to generate the spread spectrum clock signal. The open-loop ICO is part of the spread spectrum generator and in one embodiment of the invention receives feedback current signals representing the modulation method and modulation ratio. This ensures that the modulated clock output tracks the PLL output frequency. In a second embodiment the closed-loop VCO receives from the spread spectrum generator the feedback current signal representing the modulation method (center/down spread) while the open-loop VCO receives the feedback signal representing the modulation ratio.

Abstract: This sensor circuit and method for defending against tampering with an integrated circuit die uses metal wire loops to protect the circuitry. In addition, these metal wire loops have several via pairs along its length. One of the vias of the via pair goes to a NAND gate which detects a break in a section of a metal wire loop. A second via of the via pair is used to periodically discharge a metal wire loop to remove residual charge, in preparation for charging the metal wire loop and detecting any uncharged section. A given integrated circuit can have one or more metal wire loops on top of the circuitry to be protected. Each metal wire loop has one or more NAND gates. These outputs of the NAND gates can be fed into OR gates to produce an overall signal which activates an alarm or other security action such as erasure of electrically erasable programmable read only memory (EEPROM).