Abstract: An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

Abstract: An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

Abstract: An apparatus is disclosed for the optical generation of clock signals with tunable frequency and low jitter. A laser source serves as both the carrier used to transmit the clock signal for use by other optical, electronic or hybrid circuit elements and the original modulation time base. A fraction of the original laser source undergoes one or more stages of frequency division before being recombined as a modulation signal with the remaining laser beam. Transmission of the resulting signal via single mode fiber and dividers retains the low jitter properties of the modulated signal. By starting with a clock signal of optical frequency then dividing downward in frequency, comparatively high frequency clocks may be generated, notably in the GigaHertz and TeraHertz frequency ranges.

Abstract: A solar energy harvesting and storage system is disclosed having a dual-sided lithographically integrated light-to-electrical energy converter. The integrated light-to-electrical energy converter has a dual-sided photovoltaic cell, a compound optical structure and a plurality of integrated DC to AC converters. Also disclosed is a dual-axis solar tracking system upon which the dual-sided lithographically integrated light-to-electrical energy converter is mounted. The dual-axis solar tracking system has two stages of tracking mounts, each tracking mount has a plurality of leaf-springs in a vertical arrangement. The leaf springs have differential coefficients of expansion and contraction so that each tracking mount tracks a solar light source in an orthogonal direction from the other tracking mount.

Abstract: A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic.

Abstract: An apparatus is disclosed for the optical generation of clock signals with tunable frequency and low jitter. A laser source serves as both the carrier used to transmit the clock signal for use by other optical, electronic or hybrid circuit elements and the original modulation time base. A fraction of the original laser source undergoes one or more stages of frequency division before being recombined as a modulation signal with the remaining laser beam. Transmission of the resulting signal via single mode fiber and dividers retains the low jitter properties of the modulated signal. By starting with a clock signal of optical frequency then dividing downward in frequency, comparatively high frequency clocks may be generated, notably in the GigaHertz and TeraHertz frequency ranges.

Abstract: A method for increasing simulation speed is achieved by implementing a sequence of executable embodiments of digital, analog, mixed-signal or full-wave components are substituted during the process. The substituted embodiments represent more optimal instruction sequences, reconfigurable logic configurations or combinations thereof which may only be a valid representation of the model being simulated, subject to specific operating conditions.

Abstract: An innovative method is taught for accelerating the simulation rate of differential equation systems having behavior piece-wise continuous in both value and time. Specifically, a system of differential equations representing the behavior of a physical system comprised of electronic, optical, or mechanical components may be simulated more rapidly using this method. The method utilizes incremental and iterative reconfiguration of digital logic wherein each configuration of the logic operates to yield a unique future value or range of values for each time-varying state variable within a system of equations representing a linear approximation of the original differential equation system for state variable values defined initially or at the onset of an iteration. Various configurations of the digital logic may be pre-computed or computed on demand, optionally caching such configurations for subsequent reuse.

Abstract: A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic.

Abstract: A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models. The innovative method taught here incrementally generates processor instructions optimized for operating the analog solver around a specific set of values (the operating context), caches sequences and applies the currently applicable operating context at each point in the simulation. The invention discloses a method for semi-automatically generating a mixed-signal or analog model based on iterative probing of an existing device or behavioral simulation. The invention teaches a method for model abstraction to alter the level of detail present in a running simulation. A means for graphically evaluating the match quality constitutes the final innovative step.

Abstract: A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target, a FPGA, system-on-a-chip or custom logic.

Abstract: A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models. The innovative method taught here incrementally generates processor instructions optimized for operating the analog solver around a specific set of values (the operating context), caches sequences and applies the currently applicable operating context at each point in the simulation. The invention discloses a method for semi-automatically generating a mixed-signal or analog model based on iterative probing of an existing device or behavioral simulation. The invention teaches a method for model abstraction to alter the level of detail present in a running simulation. A means for graphically evaluating the match quality constitutes the final innovative step.

Abstract: An innovative hardware/software design tool provides four modes of operation for converting an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. The first mode of operation compiles design and logic technology specifications into a model which can be utilized for behavioral analysis (such as simulation or formal verification) of logical characteristics (the model). The second mode of operation translates (compiles) partitions of the design and one or more logic technologies into one or more processor intermediates or binaries (embedded binary) suitable for execution on multi-purpose processing units (embedded or general purpose processors).

Abstract: An apparatus and method for semi-automated generation and application of language conformity tests is disclosed. Generation is based on interpretative or compiled processing of a generator-oriented, formal language specification embodying lexical, syntactic and semantics aspects of a language standard as well as specific test strategies. Such test strategies control the order and extent of the test sequence generated and applied. Both test case generation and application of test cases may occur in parallel.

Abstract: A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.