Patents Assigned to Fuji Electric Co.
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Publication number: 20250070074Abstract: A semiconductor device, including an electrically conductive portion, and a terminal. The terminal includes a bonding portion that is of a flat plate shape and has: a rear surface bonded to the electrically conductive portion, and a front surface having an indentation formed thereon. The front surface has two opposite sides that are respectively a bonding front-end side and a bonding rear-end side. The indentation has two opposite sides that are respectively an indentation front-end side and an indentation rear-end side. The indentation front-end side is flush with the bonding front-end side. A length of the indentation rear-end side is shorter than a length of the bonding rear-end side.Type: ApplicationFiled: June 27, 2024Publication date: February 27, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventor: Hiroaki HOKAZONO
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Publication number: 20250070057Abstract: A semiconductor device, having: a circuit board, including a wiring board and a semiconductor element disposed on a first surface of the wiring board; a case having a hollow portion housing the circuit board; and a first conductive terminal and a second conductive terminal attached to the case, each of the first conductive terminal and the second conductive terminal having an inner connection portion exposed to the hollow portion of the case. The inner connection portions have a first gap therebetween in the hollow portion of the case. The first conductive terminal and the second conductive terminal each have a discharge portion facing each other across a second gap narrower than the first gap. The discharge portion of the first conductive terminal and the discharge portion of the second conductive terminal protrude to a position away from other members.Type: ApplicationFiled: June 27, 2024Publication date: February 27, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventor: Hiroaki ICHIKAWA
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Publication number: 20250069963Abstract: A semiconductor device, including: a semiconductor element; a main terminal that includes a fastening portion including a fastening hole, through which the main terminal is fastenable to an external conductor by a screw and a nut, and an extending portion extending from a first side of the fastening portion toward the semiconductor element, the extending portion being electrically connected to the semiconductor element; and a case that houses the semiconductor element. The case has a recess configured to accommodate the nut fastening the main terminal through the fastening hole. The main terminal further includes a bent portion that is bent from a peripheral edge of the fastening portion at a second side thereof different from the first side, and that is disposed between a wall surface of the recess in the case and the nut fastening the main terminal through the fastening hole.Type: ApplicationFiled: June 27, 2024Publication date: February 27, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventor: Reika UCHIMI
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Patent number: 12237237Abstract: A semiconductor module includes first and second semiconductor chips including first and second main electrodes, respectively; first and second connection terminals electrically connected to the first and second main electrodes, respectively; and an insulating sheet. The first connection terminal includes a first conductor portion including a first peripheral edge and a first terminal portion extending from the first peripheral edge in plan view, and the second connection terminal includes a second conductor portion including a second peripheral edge. A part of the first conductor portion overlap a part of the second conductor portion in plan view. The insulating sheet includes an insulating portion layered between the first and second conductor portions, and a first protruding portion positioned between a tip portion of the first terminal portion and the second peripheral edge in plan view, the first protruding portion forming an angle relative to a surface of the first terminal portion.Type: GrantFiled: May 24, 2022Date of Patent: February 25, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tadahiko Sato, Norihiro Nashida
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Patent number: 12237408Abstract: Provided is a semiconductor device, comprising a semiconductor substrate and a first electrode provided above an upper surface of the semiconductor substrate. The semiconductor substrate has a first conductive type drift region. The semiconductor substrate has a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate. The semiconductor substrate has a second conductive type contact region with a higher impurity concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate. The semiconductor substrate has a trench contact that has a conductive material in an interior of a groove portion penetrating the contact region, the conductive material being in contact with at least a part of the semiconductor substrate, and connected to the first electrode.Type: GrantFiled: December 26, 2023Date of Patent: February 25, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Soichi Yoshida
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Patent number: 12237379Abstract: A method for manufacturing a nitride semiconductor device including: forming an N-type region in a nitride semiconductor layer; implanting ions of an acceptor element into a region under the N-type region in the nitride semiconductor layer; and forming a first P-type region under the N-type region by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type region includes implanting ions of a donor element into the nitride semiconductor layer such that concentration of the donor element in the N-type region is equal to or greater than concentration of the acceptor element in the first P-type region. The implanting ions of the acceptor element into a region under the N-type region includes implanting ions of the acceptor element such that concentration of the acceptor element in the first P-type region is 1×1019 cm?3 or more and 1×1021 cm?3 or less.Type: GrantFiled: January 25, 2022Date of Patent: February 25, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryo Tanaka, Yuki Ohuchi, Katsunori Ueno, Shinya Takashima
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Publication number: 20250062271Abstract: A semiconductor module, including: a stacked substrate including a plurality of circuit boards formed on an upper surface of an insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The plate-shaped portion has a roughened region in which a plurality of recessed portions are formed on the upper surface of the plate-shaped portion. The plurality of recessed portions include a plurality of first recessed portions that each has a peeling suppressing portion protruding inward to thereby narrow a width of each first recessed portion.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoko NAKAMURA, Akihiko IWAYA, Mai SAITO, Tsubasa WATAKABE
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Publication number: 20250062272Abstract: A semiconductor module, including: a stacked substrate, which includes an insulating plate, and a plurality of circuit boards formed on an upper surface of the insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a plate-shaped bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The plate-shaped bonding portion has a plurality of recessed portions formed on an upper surface thereof, each recessed portion is of a hexagonal shape in a plan view of the semiconductor module.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventors: Tsubasa WATAKABE, Akihiko IWAYA, Yoko NAKAMURA, Yuta TAMAI, Mai SAITO
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Patent number: 12230501Abstract: A method of manufacturing a semiconductor device, including preparing a semiconductor substrate having a main surface, forming a device element structure on the main surface, forming a protective film on the main surface of the semiconductor substrate to protect the device element structure, the protective film having an opening therein, forming at least one material film in a predetermined pattern on the main surface of the semiconductor substrate and in the opening of the protective film, the at least one material film being separate from the protective film by a distance of less than 1 mm, forming a resist film on the main surface of the semiconductor substrate, covering the protective film and the at least one material film, the resist film having an opening therein corresponding to an inducing region for impurity defects, and inducing the impurity defects in the semiconductor substrate, using the resist film as a mask.Type: GrantFiled: August 31, 2021Date of Patent: February 18, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoko Kodama, Motoyoshi Kubouchi
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Patent number: 12230600Abstract: A semiconductor device including: a semiconductor chip; a plurality of insulating substrates mounted with the semiconductor chip; a printed circuit board facing the plurality of insulating substrates; and a conductive member for electrically connecting the plurality of insulating substrates and the printed circuit board is provided. The printed circuit board has a first through part arranged between the plurality of insulating substrates being adjacent to each other in a top view, and a second through part different from the first through part in shape in the top view.Type: GrantFiled: July 27, 2021Date of Patent: February 18, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventors: Narumi Sato, Yuichiro Hinata
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Patent number: 12230704Abstract: A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.Type: GrantFiled: August 3, 2020Date of Patent: February 18, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yasuyuki Hoshi
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Patent number: 12230627Abstract: A semiconductor device including a first line configured to receive a power supply voltage, a second line configured to be coupled to a load of the semiconductor device, first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor, a third line coupled to the gate electrode of the first MOS transistor, and a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other.Type: GrantFiled: July 21, 2021Date of Patent: February 18, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Isao Saito
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Patent number: 12231063Abstract: This power conversion device includes a control unit that controls a switching operation of a switching element of the inverter unit. The control unit is configured to switch between frequency modulation control and phase shift control, based on the output from the output converter unit, and execute. Then, the control unit is configured to, when switching between frequency modulation control and phase shift control, execute overlap control for executing the phase shift control while executing the frequency modulation control, in a predetermined switching operation range.Type: GrantFiled: December 27, 2022Date of Patent: February 18, 2025Assignees: FUJI ELECTRIC CO., LTD., KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATIONInventors: Yukihiro Nishikawa, Masahito Shoyama, Koki Hebishima
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Publication number: 20250054718Abstract: An electromagnetic contactor comprises: fixed contact pieces 3 including fixed contacts 9; an electromagnet unit 5 to which a movable contact piece 4, the movable contact piece 4 including movable contacts 10, the movable contacts 10 coming into contact with and being separated from the fixed contacts, is joined via a contact support 11; and a hermetically sealed container 2 configured to contain the fixed contact pieces, the movable contact piece, and the electromagnet unit in the same space, wherein in the electromagnet unit 5, unit-side joining portions 25a and 25b, the unit-side joining portions 25a and 25b being joined to container-side joining portions 33 and 36 arranged on the hermetically sealed container from the direction of movement of the movable contact piece, respectively, are arranged, and flat plate-shaped spacers 34 and 37 by which an inter-contact gap G between the fixed contacts and the movable contacts is adjusted are arranged interposed between the container-side joining portion and the uType: ApplicationFiled: June 24, 2024Publication date: February 13, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventors: Koujun KONISHI, Takashi TSUTSUMI, Yuya SAKURAI, Yuma KUSANO
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Publication number: 20250055210Abstract: A press-fit terminal to be connected to a substrate having a through hole includes a press-fit portion configured to be press-fitted and held inside the through hole; and a fitting portion configured to fit to an outer surface of the substrate outside the through hole and restrict movement of the press-fit terminal in a direction in which the press-fit terminal comes off from the through hole.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventor: Makoto ISOZAKI
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Publication number: 20250054897Abstract: A semiconductor module includes a stacked substrate in which a plurality of circuit boards are arranged on an upper surface of an insulating plate, a semiconductor element arranged on an upper surface of at least one of the circuit boards, and a metal wiring board arranged on an upper surface of the semiconductor element. The metal wiring board has a first bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface, and at least one groove is provided along an outer periphery of the first bonding portion on the upper surface of the plate-shaped portion.Type: ApplicationFiled: October 31, 2024Publication date: February 13, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mai SAITO, Yoko NAKAMURA, Tsubasa WATAKABE, Akihiko IWAYA
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Publication number: 20250054899Abstract: A semiconductor module, including: a stacked substrate including a plurality of circuit boards formed on an upper surface of an insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The plate-shaped portion has a roughened region in which a plurality of recessed portions are formed on the upper surface thereof. The plurality of recessed portions include a plurality of kinds, each kind differing in at least one of a size, a shape, and a depth of the recess portions therein from another kind.Type: ApplicationFiled: October 31, 2024Publication date: February 13, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yuta TAMAI, Akihiko IWAYA, Mai SAITO, Tsubasa WATAKABE, Yoko NAKAMURA
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Publication number: 20250054901Abstract: A semiconductor device includes an insulating substrate having a plurality of wiring patterns thereon, a semiconductor chip disposed on one wiring pattern among the plurality of wiring patterns, metal wiring electrically connected to the semiconductor chip, a case having a bottom at which the insulating substrate is disposed, and an insulating encapsulating member that fills in the case from an upper surface of the insulating substrate to have a thickness sufficient to cover the semiconductor chip while leaving at least part of the metal wiring exposed.Type: ApplicationFiled: June 26, 2024Publication date: February 13, 2025Applicant: FUJI ELECTRIC CO., LTD.Inventor: Seiichi TAKAHASHI
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Patent number: 12224320Abstract: At any timing after formation of gate electrodes, particle beam irradiation is performed to a semiconductor wafer having an n?-type drift region constituted by an n?-type epitaxial layer and having an n-type impurity concentration that is higher than a target majority carrier concentration (design value) of the n?-type drift region. Point defects of a defect density corresponding to an irradiation dose of the particle beam are generated in the n?-type drift region by the particle beam irradiation, whereby an effective majority carrier concentration of the n?-type drift region is adjusted and reduced with respect to the n-type impurity concentration of the n?-type drift region, to approach the design value. After formation of the n?-type epitaxial layer, the n-type impurity concentration of the n?-type drift region may be measured, or the n?-type epitaxial layer may be formed to have an n-type impurity concentration higher than the design value.Type: GrantFiled: January 28, 2022Date of Patent: February 11, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yoshihito Ichikawa
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Patent number: 12224319Abstract: A semiconductor device includes a first-conductivity-type drift region provided in a semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.Type: GrantFiled: September 20, 2023Date of Patent: February 11, 2025Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuya Naito