Abstract: A semiconductor module includes: a sealing resin sealing an insulation circuit board so that a second metal layer is exposed to a rear plane and the rear plane is warped downward in a convex shape; and a cylindrical member including a center outer peripheral surface formed such that an upper portion is embedded in the sealing resin and including an unevenness and a lower outer peripheral surface provided below the center outer peripheral surface and smoother than the center outer peripheral surface and provided such that a bottom plane of a lower end of the lower outer peripheral surface is exposed from the rear plane of the sealing resin and the lower outer peripheral surface above the lower end of the lower outer peripheral surface is sealed by the sealing resin and is disposed near the end of the sealing resin in relation to the insulation circuit board.

Abstract: A power factor correction circuit including: an error signal generation unit configured to output a signal obtained by amplifying an error between the output voltage of a boost chopper and a referential voltage; an oscillation unit configured to output a triangular wave signal; a zero current detection unit configured to detect zero current in an inductor current of the boost chopper; a drive signal generation unit configured to generate a drive signal for the switching element based on a zero current detection signal, the error signal, and the triangular wave signal; and an input interruption detection unit configured to detect an interruption state of an AC input voltage based on the zero current detection signal. When the input interruption detection unit detects an input interruption state, the oscillation unit controls a slope of the triangular wave signal to be larger than the slope when no input interruption state is detected.

Abstract: An inner housing part has through-holes for connecting first lead pins (power supply terminal, output terminal, ground terminal) with the connector pins. The inner housing part has grooves that house second lead pins for adjusting output signals of a sensor chip. Three of the grooves each has a shape in which a distance between opposing sides of the groove is less than a diameter of the second lead pin that corresponds to the groove. The inner housing part is fixed to a case by a thermoset adhesive so as to house lead pins arranged in the case included in a sensor element. The second lead pins are fitted in the grooves, suppressing lifting of the inner housing part during curing of the adhesive.

Abstract: A control apparatus for a resonant converter that receives a direct current (DC) voltage of a bulk capacitor. The control apparatus includes a forced turn-off control circuit that receives a resonance current detection signal, which has been produced by shunting a resonance current flowing through the resonant converter and converting the shunted resonance current to a voltage, outputs a forced turn-off signal in response to the resonance current detection signal falling between a first variable threshold and a second variable threshold that is smaller than the first variable threshold, and varies the first variable threshold and the second variable threshold in accordance with an input voltage inputted to the forced turn-off control circuit by dividing the DC voltage of the bulk capacitor.

Abstract: A gate drive apparatus is provided. The gate drive apparatus includes a gate drive unit configured to drive a gate of a switching device; a parameter measuring unit configured to measure a parameter corresponding to current flowing through the switching device; a discrepancy detection unit configured to detect discrepancy between current flowing through the switching device during an on-state of the switching device and a reference value, based on the parameter; and a control unit that, if the discrepancy is not detected, switches a change speed of a gate voltage of the switching device at a timing when a reference time has elapsed since a turn-off start of the switching device during a next turn-off time period of the switching device, and if the discrepancy is detected, keeps the change speed of the gate voltage during the next turn-off time period of the switching device.

Abstract: A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions.

Abstract: A p anode layer is formed on one main surface of an n? drift layer. N+ cathode layer having an impurity concentration more than that of the n? drift layer is formed on the other main surface. An anode electrode is formed on the surface of the p anode layer. A cathode electrode is formed on the surface of the n+ cathode layer. N-type broad buffer region having a net doping concentration more than the bulk impurity concentration of a wafer and less than the n+ cathode layer and p anode layer is formed in the n? drift layer. Resistivity ?0 of the n? drift layer satisfies 0.12V0??0?0.25V0 with respect to rated voltage V0. Total amount of net doping concentration of the broad buffer region is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.

Abstract: Among trenches disposed in a striped-shape parallel to a front surface of a semiconductor substrate, a gate electrode at a gate potential is provided in a gate trench, via a gate insulating film; and in a dummy trench, a dummy gate electrode at an emitter electric potential is provided, via a dummy gate insulating film. Among mesa regions, in a first mesa region functioning as a MOS gate, a first p-type base region is provided in a surface region overall. In a second mesa region not functioning as a MOS gate, a second p-type base region is selectively provided at a predetermined interval, along a first direction. At least one of the trenches on each side of a mesa region is a gate trench and at at least one side wall of the gate trench, a MOS gate is driven. As a result, the ON voltage may be reduced.

Abstract: There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

Abstract: The purpose of the present invention is to provide a perpendicular magnetic recording medium which uses an Ru seed layer having a (002)-oriented hcp structure, and has a magnetic recording layer including a (001)-oriented L10 ordered alloy suitable to perpendicular magnetic recording. The magnetic recording medium of the present invention includes a substrate, a first seed layer containing Ru, a second seed layer containing ZnO, a third seed layer containing MgO, and a magnetic recording layer containing an ordered alloy, in this order, the first seed layer having the (002)-oriented hexagonal closest packed structure.

Abstract: A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a gate trench portion extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction; a first-conductivity-type accumulation region provided above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region and in contact with the gate trench portion; and a second-conductivity-type floating region provided below the accumulation region and in contact with the gate trench portion, and provided in a part of the mesa portion in the array direction.

Abstract: A front surface element structure is formed on the front surface side of an n?-type semiconductor substrate. Then defects are formed throughout an n?-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n?-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n?-type semiconductor substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a mesa portion provided inside the semiconductor substrate and in contact with the gate trench portion, wherein the mesa portion has, at an end portion of an upper surface thereof, a shoulder portion in contact with the gate trench portion, the shoulder portion has an outwardly convex shape, the mesa portion has a first conductivity type emitter region that: is in contact with the gate trench portion and positioned between the upper surface of the semiconductor substrate and the drift region; and has a doping concentration higher than the drift region, a lower end of the emitter region at a position in contact with the gate trench portion is located at a deeper position in the depth direction than a lower end of the emitter region at a middle, in the transverse direction, of the mesa portion.

Abstract: A reset circuit includes: an output circuit that outputs a reset release signal for releasing reset of a reset target circuit that is to be applied with a power supply voltage, when a first voltage that rises with a rise in the power supply voltage reaches a first reference voltage that rises with a rise in the power supply voltage until the first reference voltage reaches a target level; and an inhibit circuit that inhibits the reset release signal from being output to the reset target circuit until the power supply voltage reaches a third level, the third level being higher than a first level at a time when the first reference voltage exceeds the first voltage, the third level being lower than a second level at a time when the first voltage reaches the target level.

Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: A semiconductor device including: an output element including a power supply side electrode region and an output side electrode region and configured to flow main current between the power supply side electrode region and the output side electrode region; an internal circuit including a sensor circuit configured to detect an abnormality; and a package in which the output element and the internal circuit are built, the package including a primary lead terminal and a secondary lead terminal, wherein the primary lead terminal electrically draws out an intermediate node in wiring of a primary detection circuit constituting the sensor circuit to an outside, the secondary lead terminal electrically draws out a terminal of a secondary detection circuit separable from the primary detection circuit to the outside, and depending on a connection state between the primary and secondary lead terminals, a reference value for detecting the abnormality can be changed.

Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

Abstract: A region of a portion directly beneath an OC pad is a sensing effective region in which unit cells of a current sensing portion are disposed. A p-type low-dose region is provided on a front surface of a semiconductor substrate and surrounds a periphery of the sensing effective region. The p-type low-dose region is fixed at an electric potential of a source pad of a main semiconductor element. The p-type low-dose region is disposed to be separated from a p-type base region of the sensing effective region by an n?-type region between the p-type low-dose region and the sensing effective region. A total dose of impurities in the p-type low-dose region is lower than a total dose of impurities in a p-type region of a front side of a semiconductor substrate in a main effective region in which unit cells of the main semiconductor element are disposed.

Abstract: A semiconductor device includes a power semiconductor chip, a threshold setting unit and a breaker circuit. The power semiconductor chip is connected between an output terminal and an earth terminal, and is configured to be turned on or off according to a potential at a gate terminal thereof. The threshold setting unit outputs an interrupt signal upon detecting that a voltage of a control signal received at an input terminal is lower than a predetermined voltage. The breaker circuit is connected between the gate terminal and the earth terminal, and switches on upon receiving the interrupt signal to thereby turn off the power semiconductor chip. The threshold setting unit includes a feed circuit that is configured to supply an electric charge stored in gate capacitance of the power semiconductor chip to the threshold setting unit responsive to a sudden drop of the voltage of the control signal.